Clock DescriptionMPC5606S Microcontroller Reference Manual, Rev. 7208 Freescale Semiconductor8.4.4.2.2 Auxiliary clock dividersThe selected auxiliary clock can be optionally divided before use.8.4.4.2.3 Dividers functional descriptionDividers are used for the generation of divided system and peripheral clocks. The MC_CGM has thefollowing control registers for built-in dividers:• Section 8.4.3.1.4, System Clock Divider Configuration Registers (CGM_SC_DC0…2)• Section 8.4.3.1.7, Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)• Section 8.4.3.1.9, Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)The reset value of all counters is 1. If a divider has its DE bit in the respective configuration register set to0 (the divider is disabled), any value in its DIVn field is ignored.8.4.4.3 Output clock multiplexingThe MC_CGM contains a multiplexing function for a number of clock sources which can then be used asoutput clock sources. The selection is done via the CGM_OCDS_SC register.Figure 8-18. MC_CGM Output Clock Multiplexer and PH[4] Generation8.4.4.4 Output Clock Division SelectionThe MC_CGM provides the following output signals for the output clock generation:• PH[4] (see Figure 8-18). This signal is generated by using one of the 3-stage ripple counter outputsor the selected signal without division. The non-divided signal is not guaranteed to be 50% dutycycle by the MC_CGM.• The MC_CGM also has an output clock enable register (see Section 8.4.3.1.1, Output ClockEnable Register (CGM_OC_EN)), which contains the output clock enable/disable control bit.CGM_OCDS_SC.SELCTL CGM_OCDS_SC.SELDIV0123Register Register16 MHz internal RC oscillator 04–16 MHz external oscillator 1Primary FMPLL 2Secondary FMPLL 3128 kHz internal RC oscillator 432 kHz external oscillator 5PH[4]’0’CGM_OC_EN Register
