LIN Controller (LINFlex)MPC5606S Microcontroller Reference Manual, Rev. 7Freescale Semiconductor 84523.7.2.4 LIN error status register (LINESR)Address: Base + 0x000C Access: User read/write0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R SZF OCF BEF CEF SFEF BDEF IDPEF FEF BOF 0 0 0 0 0 0 NFW w1c w1c w1c w1c w1c w1c w1c w1c w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 23-10. LIN error status register (LINESR)Table 23-9. LINESR field descriptionsField Description0:15 ReservedSZF16Stuck at Zero FlagThis bit is set by hardware when the bus is dominant for more than a 100-bit time. If the dominantstate continues, SZF flag is set again after 87-bit time. It is cleared by software.OCF17Output Compare Flag0 No output compare event occurred1 The content of the counter has matched the content of OC1[0:7] or OC2[0:7] in LINOCR. If thisbit is set and IOT bit in LINTCSR is set, LINFlex moves to Idle state.If LTOM bit in LINTCSR is set, then OCF is cleared by hardware in Initialization mode. If LTOM bit iscleared, then OCF maintains its status whatever the mode is.BEF18Bit Error FlagThis bit is set by hardware and indicates to the software that LINFlex has detected a bit error. Thiserror can occur during response field transmission (Slave and Master modes) or during headertransmission (in Master mode).This bit is cleared by software.CEF19Checksum Error FlagThis bit is set by hardware and indicates that the received checksum does not match the hardwarecalculated checksum.This bit is cleared by software.Note: This bit is never set if CCD or CFD bit in LINCR1 is set.SFEF20Synch Field Error FlagThis bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field).BDEF21Break Delimiter Error FlagThis bit is set by hardware and indicates that the received Break Delimiter is too short (less than onebit time).
