Display Control Unit (DCU)MPC5606S Microcontroller Reference Manual, Rev. 7400 Freescale Semiconductor12.3.4.43 Soft Lock HSYNC/VSYNC PARA RegisterFigure 12-52 represents the Soft Lock HSYNC/VSYNC register.Figure 12-52. Soft Lock HSYNC/VSYNC PARA RegisterTable 12-46. Soft Lock DISP_SIZE Register field descriptionsField Description0WEN_DISPWrite Enable for Soft Lock Bit SLB_DISP0 SLB is not modified1 Value is written to SLB4SLB_DISPSoft Lock Bit for DISP_SIZE Register. This bit cannot be cleared once set by software. Can onlybe cleared by system reset.0 Associated protected register is not locked and writeable1 Associated protected register is locked for write accessOffset: 0x310 Access: User read/write0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R 0 0 0 0SLB_HSYNCSLB_VSYNC 0 0 0 0 0 0 0 0 0 0WWEN_HSYNCWEN_VSYNCReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Table 12-47. Soft Lock HSYNC/VSYNC PARA Register field descriptionsField Description0WEN_HSYNCWrite Enable for Soft Lock Bit SLB_HSYNC0 SLB is not modified1 Value is written to SLB1WEN_VSYNCWrite Enable for Soft Lock Bit SLB_VSYNC0 SLB is not modified1 Value is written to SLB4SLB_HSYNCSoft Lock Bit for HSYNC Register.0 Associated protected register is not locked and writeable1 Associated protected register is locked for write access5SLB_VSYNCSoft Lock Bit for VSYNC Register.0 Associated protected register is not locked and writeable1 Associated protected register is locked for write access
