System Timer Module (STM)MPC5606S Microcontroller Reference Manual, Rev. 71222 Freescale Semiconductor39.3.2 Register descriptionsThe following sections detail the individual registers within the STM programming model.39.3.2.1 STM Control Register (STM_CR)The STM Control Register (STM_CR) includes the prescale value, freeze control and timer enable bits.Table 39-1. STM memory mapAddressOffset Register Name Register description Size(bits) Access Location0x0000 STM_CR STM Control Register 32 R/W on page 12220x0004 STM_CNT STM Counter Value 32 R/W on page 12230x0008 Reserved0x000C Reserved0x0010 STM_CCR0 STM Channel 0 Control Register 32 R/W on page 12240x0014 STM_CIR0 STM Channel 0 Interrupt Register 32 R/W on page 12240x0018 STM_CMP0 STM Channel 0 Compare Register 32 R/W on page 12250x001C Reserved0x0020 STM_CCR1 STM Channel 1 Control Register 32 R/W on page 12240x0024 STM_CIR1 STM Channel 1 Interrupt Register 32 R/W on page 12240x0028 STM_CMP1 STM Channel 1 Compare Register 32 R/W on page 12250x002C Reserved0x0030 STM_CCR2 STM Channel 2 Control Register 32 R/W on page 12240x0034 STM_CIR2 STM Channel 2 Interrupt Register 32 R/W on page 12240x0038 STM_CMP2 STM Channel 2 Compare Register 32 R/W on page 12250x003C Reserved0x0040 STM_CCR3 STM Channel 3 Control Register 32 R/W on page 12240x0044 STM_CIR3 STM Channel 3 Interrupt Register 32 R/W on page 12240x0048 STM_CMP3 STM Channel 3 Compare Register 32 R/W on page 12250x004C -0x3FFFReserved
