NXP Semiconductors MPC5606S Reference Manual Manual pdf 638 page image
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NXP Semiconductors MPC5606S Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
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  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Table Of Contents
  34. Table Of Contents
  35. Table Of Contents
  36. Table Of Contents
  37. Table Of Contents
  38. Table Of Contents
  39. Introduction
  40. MPC5606S family comparison
  41. Block diagram
  42. Feature details
  43. e200z0h core processor
  44. Crossbar switch (XBAR)
  45. Enhanced Direct Memory Access (eDMA)
  46. Interrupt Controller (INTC)
  47. System Integration Unit (SIU)
  48. SRAM
  49. Enhanced Modular Input/Output System (eMIOS)
  50. Analog-to-Digital Converter (ADC)
  51. Deserial Serial Peripheral Interface (DSPI)
  52. FlexCAN
  53. Serial communication interface module (LINFlex)
  54. Periodic Interrupt Timer module (PIT)
  55. Real Time Counter (RTC)
  56. Parallel Data Interface (PDI)
  57. Liquid Crystal Display (LCD) driver
  58. Stepper Motor Controller (SMC)
  59. IEEE 1149.1 JTAG Controller (JTAGC)
  60. How to use the MPC5606S documents
  61. Using the MPC5606S
  62. Software design
  63. Input/output pins
  64. Chapter 2
  65. Memory Map
  66. Package pinouts
  67. Pad configuration during reset phases
  68. Pad types
  69. System pins
  70. Functional ports
  71. Signal details
  72. Register protection
  73. Modes of operation
  74. Register description
  75. Functional description
  76. Access errors
  77. Features
  78. External signal description
  79. SWT Interrupt Register (SWT_IR)
  80. SWT Timeout Register (SWT_TO)
  81. SWT Window Register (SWT_WN)
  82. SWT Counter Output Register (SWT_CO)
  83. Overview
  84. Device-specific implementation
  85. Normal conversion operating modes
  86. Injected channel conversion
  87. Abort conversion
  88. Analog clock generator and conversion timings
  89. Programmable analog watchdog
  90. DMA functionality
  91. External decode signals delay
  92. Register descriptions
  93. Control logic registers
  94. Main Status Register (MSR)
  95. Interrupt registers
  96. Channel Pending Registers (CEOCFR[1..2])
  97. Interrupt Mask Register (IMR)
  98. Channel Interrupt Mask Register (CIMR[1..2])
  99. Watchdog Threshold Interrupt Status Register (WTISR)
  100. Watchdog Threshold Interrupt Mask Register (WTIMR)
  101. DMA registers
  102. DMA Channel Select Register (DMAR[1..2])
  103. Threshold registers
  104. Threshold Register (THRHLR[0:3])
  105. Conversion timing registers CTR[1..2]
  106. Mask registers
  107. Injected Conversion Mask Registers (JCMR[1..2])
  108. Delay registers
  109. Data registers
  110. Reset Configuration Half Word Source (RCHW)
  111. Single-chip boot mode
  112. Boot and alternate boot
  113. BAM software flow
  114. BAM resources
  115. Download and execute the new code
  116. Download start address, VLE bit and code size
  117. Download data
  118. Boot from UART
  119. Bootstrap with CAN
  120. Protocol
  121. Interrupts
  122. Main features
  123. CAN Sampler Sample Registers 0–11
  124. Enabling/disabling the CAN Sampler
  125. Baud rate generation
  126. Clock architecture
  127. Auxiliary clocks
  128. Clock gating
  129. Clock Generation Module (MC_CGM)
  130. Output clock multiplexing
  131. FXOSC external oscillator
  132. KHz OSC digital interface
  133. SIRC digital interface
  134. Modulation Register (MR)
  135. Normal mode with frequency modulation
  136. Powerdown mode
  137. Clock Monitor Unit (CMU)
  138. Crystal clock monitor
  139. Memory map and register description
  140. Control Status Register (CMU_CSR)
  141. Frequency Display Register (CMU_FDR)
  142. Low Frequency Reference Register FMPLL0 (CMU_LFREFR)
  143. Measurement Duration Register (CMU_MDR)
  144. Device-specific information
  145. eMIOS clocking configuration
  146. Unified Channel block
  147. Unified Channel memory map
  148. eMIOS200 Global FLAG Register (EMIOSGFLAG)
  149. eMIOS200 Output Update Disable (EMIOSOUDIS)
  150. eMIOS200 Disable Channel (EMIOSUCDIS)
  151. eMIOS200 UC A Register (EMIOSA[n])
  152. eMIOS200 UC B Register (EMIOSB[n])
  153. eMIOS200 UC Counter Register (EMIOSCNT[n])
  154. eMIOS200 UC Status Register (EMIOSS[n])
  155. Unified Channel (UC)
  156. UC modes of operation
  157. Input Programmable Filter (IPF)
  158. Clock Prescaler (CP)
  159. Effect of Freeze on the Unified Channel
  160. Effect of Freeze on the GCP
  161. Coherent accesses
  162. General operation
  163. Slave ports
  164. Slave mode
  165. Signal names and descriptions
  166. DSPI Transfer Count Register (DSPIx_TCR)
  167. DSPI Status Register (DSPIx_SR)
  168. DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
  169. DSPI POP RX FIFO Register (DSPIx_POPR)
  170. DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn)
  171. Serial Peripheral Interface (SPI) configuration
  172. SPI Master mode
  173. Receive First In First Out (RX FIFO) buffering mechanism
  174. DSPI baud rate and clock delay generation
  175. Baud rate generator
  176. Transfer formats
  177. Classic SPI transfer format (CPHA = 0)
  178. Classic SPI transfer format (CPHA = 1)
  179. Modified SPI transfer format (MTFE = 1, CPHA = 0)
  180. Modified SPI transfer format (MTFE = 1, CPHA = 1)
  181. Continuous selection format
  182. Clock polarity switching between DSPI transfers
  183. Continuous serial communications clock
  184. Interrupts/DMA requests
  185. Transmit FIFO underflow interrupt request (TFUF)
  186. Module Disable mode
  187. Baud rate settings
  188. Delay settings
  189. Detailed signal descriptions
  190. Memory map and register definition
  191. Register summary
  192. Control Descriptor L0_2 Register
  193. Control Descriptor L0_3 Register
  194. Control Descriptor L0_4 Register
  195. Control Descriptor L0_5 Register
  196. Control Descriptor L0_6 Register
  197. Control Descriptor L0_7 Register
  198. Control Descriptor Cursor 2 Register (CtrlDescCursor_2)
  199. Control Descriptor Cursor 3 Register (CtrlDescCursor_3)
  200. DCU Mode Register (DCU_MODE)
  201. BGND Register
  202. DISP_SIZE Register
  203. HSYN_PARA Register
  204. SYN_POL Register
  205. Threshold Register
  206. Interrupt Status Register (INT_STATUS)
  207. Interrupt Mask Register (INT_MASK)
  208. COLBAR Registers
  209. Divide Ratio (DIV_RATIO) register
  210. SIGN_CALC_1 Register
  211. SIGN_CALC_2 Register
  212. PDI Status Register
  213. PDI Status Mask Register
  214. Parameter Error Status (PARR_ERR) register
  215. Mask PARR_ERR Status register
  216. THRESHOLD_INP_BUF_1 Register
  217. LUMA Component Register
  218. Red Chroma Components
  219. Blue Chroma Component Register
  220. CRC_POS Register
  221. FG0_bcolor
  222. Global Protection Register
  223. Soft Lock Bit Register L0
  224. Soft Lock Bit Register L1
  225. Soft Lock DISP_SIZE Register
  226. Soft Lock HSYNC/VSYNC PARA Register
  227. Soft Lock POL Register
  228. Soft Lock L1_TRANSP Register
  229. TFT LCD panel configuration
  230. DCU mode selection and background color
  231. Layer configuration and blending
  232. Control Descriptors
  233. Graphics and data format
  234. Alpha and Chroma-key blending
  235. 16 Freescale Semiconductor
  236. Transparency mode and blending
  237. Luminance mode
  238. Hardware cursor
  239. CLUT/Tile RAM
  240. Gamma correction
  241. Synchronizing to panel frame rate
  242. Error detection
  243. List of protected registers
  244. CRC area description
  245. Programming for Debug mode
  246. ITU-R BT.656 sync information extraction
  247. PDI interface description
  248. PDI interaction with other modules
  249. Modes of operation based on sync extraction
  250. Mode of operation depending on PDI_datain
  251. PDI-related interrupts
  252. Glossary
  253. DMA channels with no triggering capability
  254. Initialization/application information
  255. Enabling a source without periodic triggering
  256. Disabling a source
  257. Microarchitecture summary
  258. Integer unit features
  259. Unimplemented SPRs and Read-only SPRs
  260. Information specific to this device
  261. Memory map/register definition
  262. DMA Error Status (DMAES) register
  263. DMA Enable Request (DMAERQH, DMAERQL) registers
  264. DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) registers
  265. DMA Set Enable Request (DMASERQ) register
  266. DMA Clear Enable Request (DMACERQ) register
  267. DMA Clear Enable Error Interrupt (DMACEEI) register
  268. DMA Clear Interrupt Request (DMACINT) register
  269. DMA Set START Bit (DMASSRT) register
  270. DMA Interrupt Request (DMAINTH, DMAINTL) registers
  271. DMA Error (DMAERRH, DMAERRL) registers
  272. DMA Hardware Request Status (DMAHRSH, DMAHRSL) registers
  273. DMA General Purpose Output Register (DMAGPOR) register
  274. DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63} registers
  275. Transfer Control Descriptor (TCD)
  276. DMA basic data flow
  277. DMA performance
  278. DMA programming errors
  279. DMA arbitration mode considerations
  280. Fixed group arbitration, round-robin channel arbitration
  281. Multiple requests
  282. TCD status
  283. Preemption status
  284. Dynamic programming
  285. Hardware request release timing
  286. Processor Core Type (PCT) register
  287. Miscellaneous Wakeup Control Register (MWCR)
  288. Miscellaneous Interrupt Register (MIR)
  289. Miscellaneous User-Defined Control Register (MUDCR)
  290. ECC registers
  291. ECC Status Register (ESR)
  292. ECC Error Generation Register (EEGR)
  293. Flash ECC Address Register (FEAR)
  294. Flash ECC Master Number Register (FEMR)
  295. Flash ECC Data Register (FEDR)
  296. RAM ECC Address Register (REAR)
  297. RAM ECC Master Number Register (REMR)
  298. RAM ECC Data Register (REDR)
  299. High-priority enables
  300. Flash module sectorization
  301. User mode operation
  302. Reset
  303. Power-Down mode
  304. Module Configuration Register (MCR)
  305. Low/Mid Address Space Block Locking Register (LML)
  306. 17.2.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (NVLML
  307. High Address Space Block Locking Register (HBL)
  308. Secondary Low/Mid Address Space Block Locking Register (SLL)
  309. Low/Mid aDdress Space Block Select Register (LMS)
  310. High Address Space Block Select Register (HBS)
  311. Address Register (ADR)
  312. Bus Interface Unit 0 register (BIU0)
  313. Bus Interface Unit 2 register (BIU2)
  314. User Test 0 register (UT0)
  315. User Test 1 register (UT1)
  316. User Test 2 register (UT2)
  317. User Multiple Input Signature Register 1 (UMISR1)
  318. User Multiple Input Signature Register 2 (UMISR2)
  319. User Multiple Input Signature Register 4 (UMISR4)
  320. Non-volatile private censorship PassWord 0 register (NVPWD0)
  321. Non-Volatile Private Censorship Password 1 Register (NVPWD1)
  322. Non-Volatile System Censoring Information 1 register (NVSCI1)
  323. Non-Volatile User Options register (NVUSRO)
  324. Programming considerations
  325. Error Correction Code (ECC)
  326. 17.3.6.3 Non-Volatile Low/Mid Address Space Block Locking Register (NVLML
  327. User Multiple Input Signature Register 0 (UMISR0)
  328. User Multiple Input Signature Register 3 (UMISR3)
  329. Double Word program
  330. Sector erase
  331. User Test mode
  332. EEPROM emulation
  333. Censored mode
  334. Access protections
  335. Read cycles—buffer hit
  336. Access pipelining
  337. Bank1 temporary holding registers
  338. Read-While-Write functionality
  339. Wait-State emulation
  340. Timing diagrams
  341. Initialization / application information
  342. Flash memory setting recommendations
  343. FlexCAN module features
  344. Signal descriptions
  345. Message Buffer structure
  346. Rx FIFO Structure
  347. Control Register (CTRL)
  348. Free Running Timer (TIMER)
  349. Rx Global Mask (RXGMASK)
  350. Rx 14 Mask (RX14MASK)
  351. Error and Status Register (ESR)
  352. Interrupt Mask Register High (IMRH)
  353. Interrupt Mask Register Low (IMRL)
  354. Interrupt Flag Register High (IFRH)
  355. Rx Individual Mask Registers (RXIMR0–RXIMR63)
  356. Transmit process
  357. Receive process
  358. Matching process
  359. Data coherence
  360. Message Buffer deactivation
  361. Rx FIFO
  362. CAN protocol related features
  363. Overload frames
  364. Arbitration and matching timing
  365. Modes of operation: details
  366. FlexCAN Addressing and RAM size configurations
  367. Bypass mode
  368. Instruction register
  369. Boundary Scan register
  370. TAP Controller state machine
  371. Selecting an IEEE 1149.1-2001 register
  372. BYPASS instruction
  373. IDCODE instruction
  374. e200z0 OnCE controller
  375. e200z0 OnCE controller register description
  376. START Signal
  377. Slave Address Transmission
  378. Repeated START Signal
  379. Handshaking
  380. Generation of stop
  381. Generation of repeated START
  382. DMA application information
  383. Software vector mode
  384. Stop mode
  385. INTC Module Configuration Register (INTC_MCR)
  386. INTC Interrupt Acknowledge Register (INTC_IACKR)
  387. INTC End-of-Interrupt Register (INTC_EOIR)
  388. Interrupt Request Sources
  389. Peripheral Interrupt Requests
  390. Last-In First-Out (LIFO)
  391. Handshaking with processor
  392. Hardware vector mode handshaking
  393. ISR, RTOS, and task hierarchy
  394. Order of execution
  395. Priority Ceiling Protocol
  396. Software configurable interrupt requests
  397. Scheduling an ISR on another processor
  398. Proper setting of interrupt request priority
  399. LCD Prescaler Control Register (LCDPCR)
  400. LCD Contrast Control Register (LCDCCR)
  401. LCD Frontplane Enable Register 0 (FPENR0)
  402. LCD Frontplane Enable Register 1 (FPENR1)
  403. LCDRAM (Location 0)
  404. LCDRAM (Location 1)
  405. LCDRAM (Location 2)
  406. LCDRAM (Location 3)
  407. LCDRAM (Location 4)
  408. LCDRAM (Location 5)
  409. LCDRAM (Location 6)
  410. LCDRAM (Location 7)
  411. LCDRAM (Location 8)
  412. LCDRAM (Location 9)
  413. LCDRAM (Location 10)
  414. LCDRAM (Location 11)
  415. LCDRAM (Location 12)
  416. LCDRAM (Location 13)
  417. LCDRAM (Location 14)
  418. LCDRAM (Location 15)
  419. LCD clock and frame frequency
  420. Contrast adjustment
  421. LCD RAM
  422. LCD bias and modes of operation
  423. Operation in power saving modes
  424. Boost at switching
  425. LCD waveform examples
  426. duty multiplexed with 1/2 Bias mode
  427. Duty multiplexed with 1/3 Bias mode
  428. Duty multiplexed with 1/3 Bias
  429. Initialization information
  430. Features common to LIN and UART
  431. Fractional baud rate generation
  432. Operating modes
  433. Low-power mode (Sleep)
  434. Memory map and registers description
  435. LIN control register 1 (LINCR1)
  436. LIN interrupt enable register (LINIER)
  437. LIN status register (LINSR)
  438. LIN error status register (LINESR)
  439. UART mode control register (UARTCR)
  440. UART mode status register (UARTSR)
  441. LIN timeout control status register (LINTCSR)
  442. LIN output compare register (LINOCR)
  443. LIN fractional baud rate register (LINFBRR)
  444. LIN integer baud rate register (LINIBRR)
  445. LIN checksum field register (LINCFR)
  446. Buffer identifier register (BIDR)
  447. Buffer data register LSB (BDRL)
  448. Identifier filter enable register (IFER)
  449. Identifier filter match index (IFMI)
  450. Identifier filter mode register (IFMR)
  451. Identifier filter control register (IFCR2n)
  452. Identifier filter control register (IFCR2n + 1)
  453. Register map and reset values
  454. UART mode
  455. UART transmitter
  456. Slave mode with identifier filtering
  457. Slave mode with automatic resynchronization
  458. Output compare mode
  459. MPU Error Address Register, Slave Port n (MPU_EARn)
  460. MPU Error Detail Register, Slave Port n (MPU_EDRn)
  461. MPU Region Descriptor n (MPU_RGDn)
  462. 24.2.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn
  463. Access evaluation—hit determination
  464. Putting It All Together and AHB Error Terminations
  465. Mode Control Register (ME_MCTL)
  466. Mode Enable Register (ME_ME)
  467. Interrupt Status Register (ME_IS)
  468. Interrupt Mask Register (ME_IM)
  469. Invalid Mode Transition Status Register (ME_IMTS)
  470. Debug Mode Transition Status Register (ME_DMTS)
  471. Reset Mode Configuration Register (ME_RESET_MC)
  472. Test Mode Configuration Register (ME_TEST_MC)
  473. DRUN Mode Configuration Register (ME_DRUN_MC)
  474. Run0...3 Mode Configuration Registers (ME_RUN0...3_MC)
  475. Stop Mode Configuration Register (ME_STOP_MC)
  476. Peripheral Status Register 0 (ME_PS0)
  477. Peripheral Status Register 1 (ME_PS1)
  478. Peripheral Status Register 2 (ME_PS2)
  479. Run Peripheral Configuration Registers (ME_RUN_PC0...7)
  480. Low-Power Peripheral Configuration Registers (ME_LP_PC0...7)
  481. Peripheral Control Registers (ME_PCTL0...143)
  482. Mode details
  483. Test mode
  484. Run0...3 modes
  485. Standby mode
  486. Target mode request
  487. Peripheral Clocks Disable
  488. Processor Low-Power mode entry
  489. Flash Modules Switch-On
  490. Peripheral Clocks Enable
  491. Power Domain #2 Switch-Off
  492. FMPLL0 Switch-Off
  493. Current mode update
  494. Protection of mode configuration registers
  495. Safe mode transition interrupt
  496. Application Example
  497. Operating mode
  498. Port Configuration Register (PCR)
  499. Development Control Register 1, 2 (DC1, DC2)
  500. Development Status Register (DS)
  501. Read/Write Access Control/Status (RWCS)
  502. Read/Write Access Address (RWA)
  503. Watchpoint Trigger Register (WT)
  504. Enabling Nexus clients for TAP access
  505. Configuring the NDI for Nexus messaging
  506. Nexus messaging
  507. Signal description
  508. Current Timer Value (CVAL) register
  509. Timer Control (TCTRL) register
  510. Debug mode
  511. Read Cycles
  512. Power Domain #1 Configuration Register (PCU_PCONF1)
  513. Power Domain Status Register (PCU_PSTAT)
  514. Mode transitions
  515. Standby mode transition
  516. Power saving for memories during Standby mode
  517. Preface
  518. Glossary for QuadSPI module
  519. QuadSPI modes of operation
  520. Debug mode (SPI modes only)
  521. Detailed Signal Description
  522. QSPI_IO2—QuadSPI Data IO_2
  523. AMBA bus register memory map
  524. IP bus register descriptions
  525. Transfer Count Register (QSPI_TCR)
  526. SPI Status Register (QSPI_SPISR)
  527. PUSH TX FIFO Register (QSPI_PUSHR)
  528. POP RX FIFO Register (QSPI_POPR)
  529. Transmit FIFO Registers 0 – 14 (QSPI_TXFR0 – QSPI_TXFR14)
  530. RX FIFO Registers 0 – 14 (QSPI_RXFR0 – QSPI_RXFR14)
  531. Instruction Code Register (QSPI_ICR)
  532. Sampling Register (QSPI_SMPR)
  533. RX Buffer Status Register (QSPI_RBSR)
  534. RX Buffer Data Registers 0–14 (QSPI_RBDR0–QSPI_RBDR14)
  535. TX Buffer Status Register (QSPI_TBSR)
  536. TX Buffer Data Register (QSPI_TBDR)
  537. Serial Flash Mode Status Register (QSPI_SFMSR)
  538. Serial Flash Mode Flag Register (QSPI_SFMFR)
  539. AHB bus register memory map descriptions
  540. AHB bus access considerations
  541. SPI (Serial Peripheral Interface) modes
  542. Start and Stop of SPI Transfers
  543. Master mode
  544. Baud Rate and Clock Delay Generation
  545. SPI Transfer Formats
  546. SPI mode interrupt and DMA requests
  547. SFM (Serial Flash) mode
  548. Issuing SFM Commands
  549. Flash Programming
  550. Byte Ordering of Serial Flash Data
  551. Serial Flash mode interrupt and DMA requests
  552. TX Buffer Operation
  553. Power saving features
  554. Leaving power-saving modes
  555. Baud rate settings—SPI modes only
  556. Delay settings—SPI modes only
  557. Oak family compatibility with the QuadSPI—SPI modes only
  558. Calculation of FIFO pointer addresses—SPI modes only
  559. 30.6.5.1 Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO
  560. Available status/flag information—SFM mode only
  561. Overview of error flags
  562. DMA usage
  563. Serial Flash Devices
  564. Supported Instruction Codes in Winbond Devices
  565. Serial Flash Clock Frequency Limitations
  566. Functional Event Status Register (RGM_FES)
  567. Destructive Event Status Register (RGM_DES)
  568. Functional Event Reset Disable Register (RGM_FERD)
  569. Destructive Event Reset Disable Register (RGM_DERD)
  570. Functional Event Alternate Request Register (RGM_FEAR)
  571. Destructive Event Alternate Request Register (RGM_DEAR)
  572. Functional Event Short Sequence Register (RGM_FESS)
  573. Standby Reset Sequence Register (RGM_STDBY)
  574. Phase0 Phase
  575. Phase1 Phase
  576. Destructive Resets
  577. Functional Resets
  578. Alternate Event Generation
  579. Device specific information
  580. Debug support
  581. RTC Control Register (RTCC)
  582. RTC Status Register (RTCS)
  583. RTC Counter Register (RTCCNT)
  584. API functional description
  585. Register memory map
  586. Reset effects on SRAM accesses
  587. Initialization and application information
  588. SOUND_DURATION register
  589. SGL_STATUS register
  590. PWM alignment modes
  591. M1C0M/M1C0P/M1C1M/M1C1P — PWM output pins for Motor 1
  592. Motor Controller Control Register 0 (MCCTL0)
  593. Motor Controller Control Register 1 (MCCTL1)
  594. Motor Controller Period Register (MCPER)
  595. Motor Controller Duty Cycle Register (MCDC0..11)
  596. Short-circuit Detector Timeout Register (MCSDTO)
  597. Short-circuit Detector Enable Register 1 (MCSDE1)
  598. Short-circuit Detector Interrupt Enable Register 0 (MCSDIEN0)
  599. Short-circuit Detector Interrupt Enable Register 2 (MCSDIEN2)
  600. Short-circuit Detector Interrupt Register 1 (MCSDI1)
  601. and PWM mode functions
  602. PWM Duty Cycle
  603. Output switching delay
  604. Interrupt Enable and Flag Register (IRQ)
  605. Integration Accumulator Register (ITGACC)
  606. Blanking Counter Load Register (BLNCNTLD)
  607. SSD Prescale and Divider Register (PRESCALE)
  608. Analog Wrapper + Port Control
  609. Register Interface
  610. BIS control
  611. Stepper Stall Detection Measurement
  612. Details of the SSD Measurement
  613. Additional modes of operation
  614. SSD startup
  615. Setting of the PRESCALE Register
  616. Offset Cancellation Considerations
  617. Stepper Motor Transition Considerations
  618. Legacy modes—separate blanking and integration phase
  619. MCU ID Register #2 (MIDR2)
  620. Interrupt Status Flag Register (ISR)
  621. Interrupt Rising-Edge Event Enable Register (IREER)
  622. Interrupt Filter Enable Register (IFER)
  623. GPIO Pad Data Output Registers (GPDO0_3–GPDO132_135)
  624. Parallel GPIO Pad Data Out Registers (PGPDO0–PGPDO4)
  625. Parallel GPIO Pad Data In Register (PGPDI0–PGPDI4)
  626. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC15)
  627. External interrupts
  628. External interrupt management
  629. System Status Register (STATUS)
  630. Error Configuration
  631. Debug Status Port Register
  632. Password Comparison Registers
  633. STM Count Register (STM_CNT)
  634. STM Channel Control Register (STM_CCRn)
  635. STM Channel Compare Register (STM_CMPn)
  636. VREG digital interface
  637. GPIO power supply configuration
  638. Power domain organization
  639. NMI Configuration Register (NCR)
  640. Wakeup/Interrupt Status Flag Register (WISR)
  641. Interrupt Request Enable Register (IRER)
  642. Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER)
  643. Wakeup/Interrupt Pullup Enable Register (WIPUER)
  644. NMI Management
  645. External Wakeups/Interrupts
  646. On-Chip Wakeups
  647. Appendix A
  648. Registers Under Protection
  649. Appendix B
  650. Register Map
  651. C.1 Changes between revisions 6 and 7
  652. C.2 Changes between revisions 5 and 6
  653. C.3 Changes between revisions 4 and 5
  654. C.4 Changes between revisions 3 and 4
  655. C.5 Changes between revisions 2 and 3
  656. C.6 Changes between revisions 1 and 2
  657. C.7 Changes between revisions 0 and 1
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This manual is suitable for:
MPC5602SMPC5604SMPC5606S
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