e200z0h CoreMPC5606S Microcontroller Reference Manual, Rev. 7464 Freescale Semiconductor• Dedicated PC incrementer supporting instruction prefetches• Branch unit with dedicated branch address adder, and small branch target buffer logic supportingsingle cycle of execution of certain branches, two cycles for all others14.2.1.3 Integer unit featuresThe e200 integer unit supports single cycle execution of most integer instructions:• 32-bit AU for arithmetic and comparison operations• 32-bit LU for logical operations• 32-bit priority encoder for count leading zero’s function• 32-bit single cycle barrel shifter for shifts and rotates• 32-bit mask unit for data masking and insertion• Divider logic for signed and unsigned divide in 5-34 clocks with minimized execution timing• 32 × 32 hardware multiplier array supports 1 to 4 cycles 32 × 32 32 multiply (early out)14.2.1.4 Load/store unit featuresThe e200 load/store unit supports load, store, and the load multiple / store multiple instructions:• 32-bit effective address adder for data memory address calculations• Pipelined operation supports throughput of one load or store operation per cycle• 32-bit interface to memory (dedicated memory interface on e200z0h)14.2.1.5 e200z0h system bus featuresThe features of the e200z0h System Bus interface are as follows:• Independent Instruction and Data Buses• AMBA AHB Lite Rev 2.0 Specification with support for ARM v6 AMBA Extensions— Exclusive Access Monitor— Byte Lane Strobes— Cache Allocate Support• 32-bit address bus plus attributes and control on each bus• 32-bit read data bus for Instruction Interface• Separate uni-directional 32-bit read data bus and 32-bit write data bus for Data Interface• Overlapped, in-order accesses14.3 Core registers and programmer’s modelThis section describes the registers implemented in the e200z0h core. It includes an overview of registersdefined by the PowerPC Book E architecture, highlighting differences in how these registers areimplemented in the e200 core, and provides a detailed description of e200-specific registers. Fulldescriptions of the architecture-defined register set are provided in the Power Architecture Book ESpecification.
