IEEE 1149.1 Test Access Port Controller (JTAGC)MPC5606S Microcontroller Reference Manual, Rev. 7718 Freescale Semiconductor19.6 External signal descriptionThe JTAGC consists of four signals that connect to off-chip development tools and allow access to testsupport functions. The JTAGC signals are outlined in Table 19-1.All four JTAG pins (TCK/TMS/TDI/TDO) are shared with GPIO pins, so that the software may configurethese pins as input/output by programming the appropriate registers.To ensure the proper working of JTAG, these registers have a reset value such that these pins behave asJTAG pins when the POR is lifted:• TDI: input/pullup• TCK: input/pullup• TMS: input/pullup• TDO: high-impedance/pull disabledOn entry to Standby mode the TDO pin goes to the high-Z/pull-disabled state. Some external debuggerconnections may expect the TDO to be in a known state during standby, so an external pullup or pulldownmay be required for correct operation when debugging Standby.NOTEThe JTAG Clock (TCK) typically operates at a frequency well below thesystem clock frequency, as specified in the MPC5606S MicrocontrollerData Sheet. In some cases, however, the system clock frequency may belowered significantly from the normal operating range. If the system clockfrequency is reduced below the frequency of TCK, it will no longer bepossible to communicate with the Nexus Port Controller Port ConfigurationRegister (NPC_PCR).19.7 Memory map and register descriptionThis section provides a detailed description of the JTAGC registers accessible through the TAP interface,including data registers and the instruction register. Individual bit-level descriptions and reset states ofeach register are included. These registers are not memory-mapped and can only be accessed through theTAP.Table 19-1. JTAG signal propertiesName I/O Function Reset StateTCK I Test clock PullupTDI I Test data in PullupTDO O Test data out High ZTMS I Test mode select Pullup
