NXP Semiconductors MC9S08SU16VFK manuals
MC9S08SU16VFK
Table of contents
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- Table Of Contents
- Table Of Contents
- Overview
- Typographic notation
- Introduction
- S08L core modules
- Memories and memory interfaces
- Security and integrity modules
- Communication interfaces
- Human-machine interfaces
- Orderable part numbers
- Memory map
- Reset and interrupt vector assignments
- Register addresses assignments
- Random-access memory (RAM)
- System register file
- Interrupts
- Interrupt stack frame
- Hardware nested interrupt
- Interrupt priority level register
- Integration and application of the IPC
- IPC memory map and register descriptions
- Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
- Interrupt Level Setting Registers n (IPC_ILRSn)
- Features
- Configuration options
- Clock module
- Internal clock source (ICS)
- kHz low-power oscillator (LPO)
- Wait mode
- Power modes behaviors
- Bandgap reference
- Pinout
- Signal description table
- Port data and data direction
- Input glitch filter
- Memory map and register definition
- Port B Data Register (PORT_PTBD)
- Port A Direction Register (PORT_PTADD)
- Port B Direction Register (PORT_PTBDD)
- Port A Pullup Enable Register (PORT_PTAPE)
- Port B Pullup/Pulldown Enable Register (PORT_PTBPE)
- Port B High Drive Strength Selection Register (PORT_PTBHD)
- Port Filter Register 0 (PORT_IOFLT0)
- Port Filter Register 1 (PORT_IOFLT1)
- Port Filter Register 2 (PORT_IOFLT2)
- Chip specific windowed COP
- System device identification (SDID)
- Computer operating properly (COP) watchdog
- System options
- RESET_b pin enable
- Module to module interconnects
- System Reset Status Register (SIM_SRS)
- System Background Debug Force Reset Register (SIM_SBDFR)
- System Device Identification Register: Low (SIM_SDIDL)
- System Options Register 2 (SIM_SOPT2)
- System Port A Pin Multiplexing Control Register: Low (SIM_MUXPTAL)
- System Port A Pin Multiplexing Control Register: High (SIM_MUXPTAH)
- System Port B Pin Multiplexing Control Register: Low (SIM_MUXPTBL)
- System Port B Pin Multiplexing Control Register: High (SIM_MUXPTBH)
- System Port C Pin Multiplexing Control Register: Low (SIM_MUXPTCL)
- System Clock Gating Control 2 Register (SIM_SCGC2)
- System Clock Gating Control 3 Register (SIM_SCGC3)
- System Clock Divider Register (SIM_SCDIV)
- System POR Register (SIM_PORREGn)
- Illegal Address Register: High (SIM_ILLAH)
- Universally Unique Identifier Register 0 (SIM_UUID0)
- Universally Unique Identifier Register 2 (SIM_UUID2)
- Universally Unique Identifier Register 4 (SIM_UUID4)
- Universally Unique Identifier Register 6 (SIM_UUID6)
- Programmer's Model and CPU Registers
- Index Register (H:X)
- Program Counter (PC)
- Addressing Modes
- Inherent Addressing Mode (INH)
- Direct Addressing Mode (DIR)
- Indexed Addressing Mode
- Indexed, 8-Bit Offset with Post Increment (IX1+)
- SP-Relative, 16-Bit Offset (SP2)
- Indexed to Direct, Post Increment
- Security mode
- HCS08 V6 Opcodes
- Instruction Set Summary
- Other flash module features
- Flash memory map
- Writing the FCLKDIV register
- Command write sequence
- Flash interrupts
- Protection
- Security
- Unsecuring the MCU using backdoor key access
- Unsecuring the MCU using BDM
- Flash command summary
- Erase Verify All Blocks command
- Erase Verify Flash Section command
- Read once command
- Program Flash command
- Program Once command
- Erase All Blocks command
- Erase flash block command
- Unsecure flash command
- Verify backdoor access key command
- Set user margin level command
- Set factory margin level command
- Flash Clock Divider Register (FTMRH_FCLKDIV)
- Flash Security Register (FTMRH_FSEC)
- Flash CCOB Index Register (FTMRH_FCCOBIX)
- Flash Status Register (FTMRH_FSTAT)
- Flash Protection Register (FTMRH_FPROT)
- Flash Common Command Object Register:High (FTMRH_FCCOBHI)
- Flash Common Command Object Register: Low (FTMRH_FCCOBLO)
- Block diagram
- FLL bypassed internal (FBI)
- Register definition
- ICS Control Register 2 (ICS_C2)
- ICS Control Register 3 (ICS_C3)
- ICS Control Register 4 (ICS_C4)
- ICS Status Register (ICS_S)
- Functional description
- FLL engaged external (FEE)
- FLL bypassed external (FBE)
- Mode switching
- Fixed frequency clock
- External reference clock monitor
- Initializing FEE mode
- Chip specific modulo timer
- Modes of Operation
- MTIM16 in Active Background Mode
- Memory Map and Register Descriptions
- MTIM16 clock configuration register (MTIM_CLK)
- MTIM16 counter register high (MTIM_CNTH)
- MTIM16 counter register low (MTIM_CNTL)
- MTIM16 modulo register high (MTIM_MODH)
- MTIM16 modulo register low (MTIM_MODL)
- MTIM16 Operation Example
- Chip specific power management controller
- Full performance mode
- VDDF
- Control Register (PMC_CTRL)
- Reset Flags Register (PMC_RST)
- Temperature Offset Step Trim Register (PMC_TPTM)
- RC Oscillator Offset Step Trim Register (PMC_RC20KTRM)
- Low Voltage Control and Status Register 1 (system 5 V) (PMC_LVCTLSTAT1)
- VREFH Low Voltage Warning (LVW) Configuration Register (PMC_VREFHLVW)
- VREGVDD
- LVR in low power mode
- High-accuracy reference voltage
- Low-power RC oscillator
- Chip specific KBI information
- KBI in Wait mode
- External signals description
- KBI Status and Control Register (KBI_SC)
- KBI Pin Enable Register (KBI_PE)
- KBI Pullup Resistor
- Chip specific cyclic redundancy check (CRC)
- Run mode
- CRC Data register: High 0 (CRC_DH0)
- CRC Data register: Low 1 (CRC_DL1)
- CRC Polynomial Register: High 1 (CRC_PH1)
- CRC Polynomial Register: High 0 (CRC_PH0)
- CRC Polynomial Register: Low 0 (CRC_PL0)
- CRC calculations
- Transpose feature
- CRC result complement
- Chip-specific ADC information
- ADC channel assignments
- ADC analog supply and reference connections
- Hardware trigger
- Analog Channel Inputs (ADx)
- Status and Control Register 2 (ADCx_SC2)
- Status and Control Register 3 (ADCx_SC3)
- Status and Control Register 4 (ADCx_SC4)
- Conversion Result High Register (ADCx_RH)
- Conversion Result Low Register (ADCx_RL)
- Compare Value High Register (ADCx_CVH)
- Completing conversions
- Power control
- Automatic compare function
- FIFO operation
- MCU wait mode operation
- Initialization information
- Pseudo-code example
- Application information
- Analog input pins
- Sources of error
- Code width and quantization error
- Linearity errors
- Code jitter, non-monotonicity, and missing codes
- CMP configuration information
- ACMP in stop mode
- CMP Features
- ANMUX Key Features
- CMP Block Diagram
- Memory Map/Register Definitions
- CMP Control Register 1 (CMP_CR1)
- CMP Filter Period Register (CMP_FPR)
- CMP Status and Control Register (CMP_SCR)
- DAC Control Register (CMP_DACCR)
- MUX Control Register (CMP_MUXCR)
- MUX Pin Enable Register (CMP_MUXPE)
- CMP Functional Modes
- Disabled Mode (# 1)
- Sampled, Non-Filtered Mode (#s 3A & 3B)
- Sampled, Filtered Mode (#s 4A & 4B)
- Windowed Mode (#s 5A & 5B)
- Windowed/Resampled Mode (# 6)
- Windowed/Filtered Mode (#7)
- Stop Mode Operation
- Low Pass Filter
- Latency Issues
- CMP Interrupts
- DAC Functional Description
- Chip specific FlexTimer module
- Signal description
- EXTCLK — FTM external clock
- Status and Control (FTMx_SC)
- Counter High (FTMx_CNTH)
- Counter Low (FTMx_CNTL)
- Modulo Low (FTMx_MODL)
- Channel Status and Control (FTMx_CnSC)
- Channel Value High (FTMx_CnVH)
- Channel Value Low (FTMx_CnVL)
- Prescaler
- Up counting
- Free running counter
- Output compare mode
- Edge-aligned PWM (EPWM) mode
- Center-aligned PWM (CPWM) mode
- Update of the registers with write buffers
- CnVH:L registers
- FTM Interrupts
- Chip specific pules width timer
- PWTIN[3:0] — pulse width timer capture inputs
- Pulse Width Timer Control and Status Register (PWTx_CS)
- Pulse Width Timer Control Register (PWTx_CR)
- Pulse Width Timer Positive Pulse Width Register: High (PWTx_PPH)
- Pulse Width Timer Positive Pulse Width Register: Loq (PWTx_PPL)
- Pulse Width Timer Negative Pulse Width Register: Low (PWTx_NPL)
- Reset overview
- Application examples
- Initialization/Application information
- Chip specific inter-integrated circuit
- I2C signal descriptions
- I2C Address Register 1 (I2C_A1)
- I2C Control Register 1 (I2C_C1)
- I2C Status register (I2C_S)
- I2C Data I/O register (I2C_D)
- I2C Control Register 2 (I2C_C2)
- I2C Stop Control and Status Register (I2C_SCS)
- I2C Range Address register (I2C_RA)
- I2C SMBus Control and Status register (I2C_SMB)
- I2C Address Register 2 (I2C_A2)
- I2C SCL Low Timeout Register High (I2C_SLTH)
- I2C Status register 2 (I2C_S2)
- I2C protocol
- Slave address transmission
- STOP signal
- Clock synchronization
- Clock stretching
- bit address
- Master-receiver addresses a slave-transmitter
- System management bus specification
- FAST ACK and NACK
- Resets
- Byte transfer interrupt
- Timeout interrupt in SMBus
- Double buffering mode
- Chip specific serial communications interface
- SCI signal descriptions
- SCI Baud Rate Register: High (SCIx_BDH)
- SCI Baud Rate Register: Low (SCIx_BDL)
- SCI Control Register 2 (SCIx_C2)
- SCI Status Register 1 (SCIx_S1)
- SCI Status Register 2 (SCIx_S2)
- SCI Control Register 3 (SCIx_C3)
- SCI Data Register (SCIx_D)
- Baud rate generation
- Send break and queued idle
- Receiver functional description
- Data sampling technique
- Receiver wake-up operation
- Interrupts and status flags
- Baud rate tolerance
- Slow data tolerance
- Fast data tolerance
- Additional SCI functions
- Loop mode
- Chip specific programmable delay block
- Mode of operation
- Continuous count mode
- PDB Control Register 1 (PDB_CTRL1)
- PDB0 Comparison Low Register (PDB_CMPL0)
- PDB0 Comparison High Register (PDB_CMPH0)
- PDB1 Comparison Low Register (PDB_CMPL1)
- PDB1 Counter High/Low (PDB_CNT1)
- External Mux Selection Register (XBAR_EXTMUX)
- XBAR Selection Register (XBAR_SELn)
- Chip specific GDU information
- PHCMP0 Control Register 0 (GDU_PHCMP0CR0)
- PHCMP0 Filter Period Register (GDU_PHCMP0FPR)
- PHCMP1 Control Register 0 (GDU_PHCMP1CR0)
- PHCMP1 Control Register 1 (GDU_PHCMP1CR1)
- PHCMP1 Filter Period Register (GDU_PHCMP1FPR)
- PHCMP1 Status and Control Register (GDU_PHCMP1SCR)
- PHCMP2 Control Register 0 (GDU_PHCMP2CR0)
- PHCMP2 Filter Period Register (GDU_PHCMP2FPR)
- Clamp Control Register (GDU_CLMPCTRL)
- I/O Control Register (GDU_IOCTRL)
- Virtual Network Phase Detection Control (GDU_PHASECTRL)
- Current Sensor and Overcurrent Protection Control Register (GDU_CURCTRL)
- LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1)
- LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)
- LIMIT0 CMP Status and Control Register (GDU_LIMIT0SCR)
- LIMIT0 DAC Control Register (GDU_LIMIT0DACCR)
- LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1)
- LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR)
- LIMIT1 CMP Status and Control Register (GDU_LIMIT1SCR)
- LIMIT1 DAC Control Register (GDU_LIMIT1DACCR)
- LIMIT CMP BIAS Register (GDU_SIGBIAS)
- Phase detection function descriptions
- OpAMP function descriptions
- OpAMP descriptions
- Predrive descriptions
- GCMP diagram
- GCMP functional modes
- Power modes
- Startup and operation
- GCMP interrupts
- Chip specific pulse width modulator
- MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors
- Alignment and compare output polarity
- Period
- Independent or complementary channel operation
- Deadtime generators
- Asymmetric PWM output
- PWM output polarity
- Generator loading
- Reload flag
- Initialization
- Fault protection
- Fault pin filter
- Automatic fault clearing
- PWM Control Register: Low (PWM_CTRLL)
- PWM Control Register: High (PWM_CTRLH)
- PWM Fault Control Register: Low (PWM_FCTRLL)
- PWM Fault Control Register: High (PWM_FCTRLH)
- PWM Fault Status Acknowledge Register: High (PWM_FLTACKH)
- PWM Output Control Register: Low (PWM_OUTL)
- PWM Output Control Register: High (PWM_OUTH)
- PWM Counter Register: High (PWM_CNTRH)
- PWM Counter Register: High (PWM_CMODH)
- PWM Value Register: High (PWM_VALnH)
- PWM Deadtime Register: Low (PWM_DTIMnL)
- PWM Disable Mapping Registers 1: Low (PWM_DMAP1L)
- PWM Disable Mapping Registers 1: High (PWM_DMAP1H)
- PWM Configure Register: High (PWM_CNFGH)
- PWM Channel Control Register: Low (PWM_CCTRLL)
- PWM Channel Control Register: High (PWM_CCTRLH)
- PWM Compare Invert Register: High (PWM_CINVH)
- Background debug controller (BDC)
- BKGD pin description
- Communication details
- BDC commands
- BDC hardware breakpoint
- Comparators A and B
- Bus capture information and FIFO operation
- Change-of-flow information
- Trigger modes
- Hardware breakpoints
- Memory map and register description
- BDC Breakpoint Match Register: High (BDC_BKPTH)
- BDC Breakpoint Register: Low (BDC_BKPTL)
- Debug Comparator A High Register (DBG_CAH)
- Debug Comparator A Low Register (DBG_CAL)
- Debug Comparator B High Register (DBG_CBH)
- Debug Comparator C High Register (DBG_CCH)
- Debug Comparator C Low Register (DBG_CCL)
- Debug FIFO Low Register (DBG_FL)
- Debug Comparator A Extension Register (DBG_CAX)
- Debug Comparator B Extension Register (DBG_CBX)
- Debug Comparator C Extension Register (DBG_CCX)
- Debug FIFO Extended Information Register (DBG_FX)
- Debug Trigger Register (DBG_T)
- Debug Status Register (DBG_S)
- Debug Count Status Register (DBG_CNT)
- Breakpoints
- Trigger selection
- Begin- and end-trigger
- FIFO
- Storing data in FIFO
- Interrupt priority
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