original value of IPM by writing 1 to the IPCSC[PULIPM] bit. In both cases, the IPMPSis a shift register functioning as a pseudo stack register for storing the IPM. When theIPM is updated, the original value is shifted into IPMPS. The IPMPS can store four levelsof IPM. If the last position of IPMPS is written, the PSF flag indicates that the IPMPS isfull. If all the values in the IPMPS were read, the PSE flag indicates that the IPMPS isempty.4.1.2.4 Integration and application of the IPCAll interrupt inputs that comes from peripheral modules are asynchronous signals. Noneof the asynchronous signals of the interrupts are routed to IPC. The asynchronous signalsof the interrupts are routed directly to SIM module to wake system clocks in stop mode.Additional care must be exercised when IRQ is reprioritized by IPC. CPU instructionsBIL and BIH need input from IRQ pin. If IRQ interrupt is masked, BIL and BIH stillwork but the IRQ interrupt will not occur.• The interrupt priority controller must be enabled to function. While inside aninterrupt service routine, some work has to be done to enable other higher priorityinterrupts. The following is a pseudo code example written in assembly language:INT_SER :BCLR INTFLAG,INTFLAG_R ; clear flag that generate interrupt. ; do the most critical part. ; which it cannot be interrupted...CLI ; global interrupt enable and nested interruptenabled. ; continue the less critical...BSET PULIPM, PULIPM_R ; restore the old IPM value before leavingRTI ; then you can return• A minimum overhead of six bus clock cycles is added inside an interrupt servicesroutine to enable preemptive interrupts.• As an interrupt of the same priority level is allowed to pass through IPC to HCS08CPU, the flag generating the interrupt must be cleared before doing CLI to enablepreemptive interrupts.InterruptsMC9S08SU16 Reference Manual, Rev. 5, 4/201758 NXP Semiconductors
