When PMC_TPTM[TRMTPEN] is set, the HTDS flag assert/de-assert threshold isdefined by the TOT[3:0] bits in the same register. For the detailed HTDS flag assert/de-assert thresholds, see the reference in TOT[3:0].Before configuring the TOT[3:0] bits, user should set PMC_CTRL[GWREN] to unlockthe write protection.14.8.7 Low-power RC oscillatorPMC integrates a low-power RC oscillator (LPO) which provides a typical 20 kHzoutput. This LPO can serve as an independent clock source for the MCU on-chipmodules such as watchdog.This RC oscillator is set to ON by default in the FPM mode, and can be controlled toOFF in the RPM mode by configuring PMC_CTRL[RC20KENSTP].The RC oscillator out frequency can be configured by user through the OSCOT[5:0] bitsin PMC_RC20KTRM register. Before writing to OSCOT[5:0], user should setPMC_CTRL[GWREN].14.9 Application information1. VREFH readinessVREFH is a high-accuracy voltage reference. It needs 3 ms to be stable afterPMC_STAT[VREFRDY] is asserted. When entering the Stop mode, VREFH isdisabled automatically. So after exiting from the Stop mode, it requires to waitenough settling time. After the PMC_VREFHCFG setting is changed, it takes sometime to get it settled. ADC or other functions using VREFH cannot work correctlyduring this transition period.2. 20 kHz LPO calibrationLPO has to be calibrated after the PMC powers up, in order to get the ±5% precision.The LPO clock is connected to SBAR (in the SIM module), and the calibration canbe achieved by using FTM1 with on-chip clock. Refer to the SIM chapter for moredetailed setting information.3. Special write enable register handlingChapter 14 Power Management Controller (PMC)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 233
