LDA $F03BThis instruction uses extended addressing because $F03B is above the zero page. In mostassemblers, the programmer does not need to specify whether an instruction is direct orextended. The assembler automatically selects the shortest form of the instruction.10.3.6 Indexed Addressing ModeIndexed addressing mode has seven variations, including five that use the 16-bit H:Xindex register pair and two that use the stack pointer as the base reference.10.3.6.1 Indexed, No Offset (IX)Instructions using the indexed, no offset addressing mode are one-byte instructions thatcan access data with variable addresses. The X (Index register low byte) register containsthe low byte of the conditional address of the operand and the H (Index register highbyte) register contains the high byte of the address.Indexed, no offset instructions can move a pointer through a table or hold the address of afrequently used RAM or input/output (I/O) location.10.3.6.2 Indexed, No Offset with Post Increment (IX+)Instructions using the indexed, no offset with post increment addressing mode are two-byte instructions that address the operands and then increment the Index register (H:X).The X (Index register low byte) register contains the low byte of the conditional addressof the operand and the H (Index register high byte) register contains the high byte of theaddress. This addressing mode is usually used for table searches. MOV and CBEQinstructions use this addressing mode as well.10.3.6.3 Indexed, 8-Bit Offset (IX1)Indexed with 8-bit offset instructions are two-byte instructions that can access data with avariable address. The CPU adds the unsigned bytes in the H:X register to the unsignedbyte immediately following the opcode. The sum is the effective address.Indexed, 8-bit offset instructions are useful in selecting the k-th element in an n-elementtable. The table can begin anywhere and can extend as far as the address map allows. Thek value would typically be in H:X, and the address of the beginning of the table would beAddressing ModesMC9S08SU16 Reference Manual, Rev. 5, 4/2017134 NXP Semiconductors
