DBG memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page18C0 Debug Comparator A High Register (DBG_CAH) 8 R/W FFh 28.3.1/55218C1 Debug Comparator A Low Register (DBG_CAL) 8 R/W FEh 28.3.2/55318C2 Debug Comparator B High Register (DBG_CBH) 8 R/W 00h 28.3.3/55418C3 Debug Comparator B Low Register (DBG_CBL) 8 R/W 00h 28.3.4/55418C4 Debug Comparator C High Register (DBG_CCH) 8 R/W 00h 28.3.5/55518C5 Debug Comparator C Low Register (DBG_CCL) 8 R/W 00h 28.3.6/55618C6 Debug FIFO High Register (DBG_FH) 8 R 00h 28.3.7/55618C7 Debug FIFO Low Register (DBG_FL) 8 R 00h 28.3.8/55718C8 Debug Comparator A Extension Register (DBG_CAX) 8 R/W 00h 28.3.9/55818C9 Debug Comparator B Extension Register (DBG_CBX) 8 R/W 00h 28.3.10/55918CA Debug Comparator C Extension Register (DBG_CCX) 8 R/W 00h 28.3.11/56018CB Debug FIFO Extended Information Register (DBG_FX) 8 R 00h 28.3.12/56118CC Debug Control Register (DBG_C) 8 R/W C0h 28.3.13/56118CD Debug Trigger Register (DBG_T) 8 R/W 40h 28.3.14/56218CE Debug Status Register (DBG_S) 8 R 01h 28.3.15/56418CF Debug Count Status Register (DBG_CNT) 8 R 00h 28.3.16/56528.3.1 Debug Comparator A High Register (DBG_CAH)NOTEAll the bits in this register reset to 1 in POR or non-end-runreset. The bits are undefined in end-run reset. In the case of anend-trace to reset where DBGEN = 1 and BEGIN = 0, the bitsin this register do not change after reset.Address: 18C0h base + 0h offset = 18C0hBit 7 6 5 4 3 2 1 0Read CA[15:8]WriteReset 1 1 1 1 1 1 1 1Memory map and registersMC9S08SU16 Reference Manual, Rev. 5, 4/2017552 NXP Semiconductors
