25.6 Memory map and register definitionThis section includes the module memory map and detailed descriptions of all registers.GDU memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page20 PHCMP0 Control Register 0 (GDU_PHCMP0CR0) 8 R/W 00h 25.6.1/43921 PHCMP0 Control Register 1 (GDU_PHCMP0CR1) 8 R/W 00h 25.6.2/43922 PHCMP0 Filter Period Register (GDU_PHCMP0FPR) 8 R/W 00h 25.6.3/44123 PHCMP0 Status and Control Register (GDU_PHCMP0SCR) 8 R/W 00h 25.6.4/44124 PHCMP1 Control Register 0 (GDU_PHCMP1CR0) 8 R/W 00h 25.6.5/44225 PHCMP1 Control Register 1 (GDU_PHCMP1CR1) 8 R/W 00h 25.6.6/44326 PHCMP1 Filter Period Register (GDU_PHCMP1FPR) 8 R/W 00h 25.6.7/44427 PHCMP1 Status and Control Register (GDU_PHCMP1SCR) 8 R/W 00h 25.6.8/44528 PHCMP2 Control Register 0 (GDU_PHCMP2CR0) 8 R/W 00h 25.6.9/44629 PHCMP2 Control Register 1 (GDU_PHCMP2CR1) 8 R/W 00h 25.6.10/4462A PHCMP2 Filter Period Register (GDU_PHCMP2FPR) 8 R/W 00h 25.6.11/4482B PHCMP2 Status and Control Register (GDU_PHCMP2SCR) 8 R/W 00h 25.6.12/4481870 Clamp Control Register (GDU_CLMPCTRL) 8 R/W 86h 25.6.13/4491871 I/O Control Register (GDU_IOCTRL) 8 R/W 01h 25.6.14/4501872 Virtual Network Phase Detection Control(GDU_PHASECTRL) 8 R/W 00h 25.6.15/4511873 Current Sensor and Overcurrent Protection Control Register(GDU_CURCTRL) 8 R/W 00h 25.6.16/4521874 LIMIT0 CMP Control Register 0 (GDU_LIMIT0CR0) 8 R/W 00h 25.6.17/4521875 LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1) 8 R/W 00h 25.6.18/4531876 LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR) 8 R/W 00h 25.6.19/4541877 LIMIT0 CMP Status and Control Register(GDU_LIMIT0SCR) 8 R/W 00h 25.6.20/4551878 LIMIT0 DAC Control Register (GDU_LIMIT0DACCR) 8 R/W 00h 25.6.21/4561879 LIMIT1 CMP Control Register 0 (GDU_LIMIT1CR0) 8 R/W 00h 25.6.22/456187A LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1) 8 R/W 00h 25.6.23/457187B LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR) 8 R/W 00h 25.6.24/458187C LIMIT1 CMP Status and Control Register(GDU_LIMIT1SCR) 8 R/W 00h 25.6.25/459187D LIMIT1 DAC Control Register (GDU_LIMIT1DACCR) 8 R/W 00h 25.6.26/460187E PDCS and Clamp Status Register (GDU_STATREG) 8 R 00h 25.6.27/460187F LIMIT CMP BIAS Register (GDU_SIGBIAS) 8 R/W 00h 25.6.28/461Memory map and register definitionMC9S08SU16 Reference Manual, Rev. 5, 4/2017438 NXP Semiconductors
