in the byte following the opcode. Using H:X in this way, this addressing mode is limitedto the first 256 addresses in memory. Tables can be located anywhere in the address mapwhen H:X is used as the base address, and the byte following the opcode is the offset.10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)Indexed, 8-bit offset with post-increment instructions are three-byte instructions thataccess the operands with variable addresses, then increment H:X. The CPU adds theunsigned bytes in the H:X register to the byte immediately following the opcode. Thesum is the effective address. This addressing mode is generally used for table searches.This addressing mode is used for CBEQ instruction.10.3.6.5 Indexed, 16-Bit Offset (IX2)Indexed, 16-bit offset instructions are three-byte instructions that can access data withvariable addresses at any location in memory. The CPU adds the unsigned contents ofH:X to the 16-bit unsigned word formed by the two bytes following the opcode. The sumis the effective address of the operand. The first byte after the opcode is the mostsignificant byte of the 16-bit offset; the second byte is the least significant byte of the 16-bit offset. As with direct and extended addressing, most assemblers determine the shortestform of indexed addressing.Indexed, 16-bit offset instructions are useful in selecting the k-th element in an n-elementtable. The table can begin anywhere and can extend as far as the address map allows. Thek value would typically be in H:X, and the address of the beginning of the table would bein the bytes following the opcode.10.3.6.6 SP-Relative, 8-Bit Offset (SP1)Stack pointer, 8-bit offset instructions are three-byte instructions that address operands inmuch the same way as indexed 8-bit offset instructions, except that the 8-bit offset isadded to the value of the stack pointer instead of the index register.The stack pointer, 8-bit offset addressing mode permits easy addressing of data on thestack. The CPU adds the unsigned byte in the 16-bit stack pointer (SP) register to theunsigned byte following the opcode. The sum is the effective address of the operand. Ifinterrupts are disabled, this addressing mode allows the stack pointer to be used as asecond "index" register.Chapter 10 Central processor unitMC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 135
