26.4.23 PWM Channel Control Register: High (PWM_CCTRLH)This write-protectable register contains the configuration bits that determine PWM modesof operation as detailed below. The ENHA bit cannot be modified after the WP bit in theCNFG register is set. ENHA in turn provides protection for the VLMODE[1:0], SWP45,SWP23 and SWP01 bits. The Mask bits are not write protectable.Address: 40h base + 17E3h offset = 1823hBit 7 6 5 4 3 2 1 0Read ENHA 1 MSKWriteReset 0 1 0 0 0 0 0 0PWM_CCTRLH field descriptionsField Description7ENHAEnable Hardware AccelerationThis bit enables writing to the VLMODE[1:0], SWP45, SWP23, and SWP01 bits. The bit is write protectedby the CNFG register WP bit.0 Disable writing to VLMODE[1:0], SWP45, SWP23, and SWP01 bits1 Enable writing to VLMODE[1:0], SWP45, SWP23, and SWP01 bits6ReservedThis field is reserved.This read-only field is reserved and always has the value 1.MSK MaskThese six bits determine the mask for each of the PWM logical channels.0 Unmasked1 Masked, channel set to a value of zero percent duty cycle26.4.24 PWM Pulse Edge Control Register: Low (PWM_PECTRLL)This register is used to control PWM pulse generation for various applications, such as apower-supply phase-shifting application.The PECn bits only apply in edge-aligned operation during complementary mode. Thesecontrol bits allow the PWM pulses generated by both the odd and even VAL regs to beXORed together prior to the complementary logic and deadtime insertion.NOTEThe PECn bits are buffered. The value written does not takeeffect until the LDOK bit is set and the next PWM load cyclebegins. Reading PECn reads the value in a buffer and notnecessarily the value the PWM generator is currently using.Memory Map and Register DescriptionsMC9S08SU16 Reference Manual, Rev. 5, 4/2017524 NXP Semiconductors
