12.1.3.3 FLL bypassed internal (FBI)In FLL bypassed internal mode, the FLL is enabled and controlled by the internalreference clock, but is bypassed. The ICS supplies a clock derived from the internalreference clock.12.1.3.4 FLL bypassed internal low power (FBILP)In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and theICS supplies a clock derived from the internal reference clock.12.1.3.5 FLL bypassed external (FBE)In FLL bypassed external mode, the FLL is enabled and controlled by an externalreference clock, but is bypassed. The ICS supplies a clock derived from the externalreference clock source.12.1.3.6 FLL bypassed external low power (FBELP)In FLL bypassed external low power mode, the FLL is disabled and bypassed, and theICS supplies a clock derived from the external reference clock.12.1.3.7 Stop (STOP)In Stop mode, the FLL is disabled. The ICS does not provide any MCU clock sources.NOTEThe DCO frequency changes from the pre-stop value to its resetvalue and the FLL needs to reacquire the lock before thefrequency is stable. Timing sensitive operations must wait forthe FLL acquisition time, tAcquire, before executing.12.2 External signal descriptionThere are no ICS signals that connect off chip.Chapter 12 Internal Clock Source (ICS)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 191
