28.3.12 Debug FIFO Extended Information Register (DBG_FX)NOTEAll the bits in this register reset to 0 in POR or non-end-runreset. The bits are undefined in end-run reset. In the case of anend-trace to reset where DBGEN = 1 and BEGIN = 0, the bitsin this register do not change after reset.Address: 18C0h base + Bh offset = 18CBhBit 7 6 5 4 3 2 1 0Read PPACC 0 Bit16WriteReset 0 0 0 0 0 0 0 0DBG_FX field descriptionsField Description7PPACCPPAGE Access Indicator BitThis bit indicates whether the captured information in the current FIFO word is associated with anextended access through the PPAGE mechanism or not. This is indicated by the internal signalmmu_ppage_sel which is 1 when the access is through the PPAGE mechanism.0 The information in the corresponding FIFO word is event-only data or an unpaged 17-bit CPU addresswith bit-16 = 0.1 The information in the corresponding FIFO word is a 17-bit flash address with PPAGE[2:0] in the threemost significant bits and CPU address[13:0] in the 14 least significant bits.6–1ReservedThis field is reserved.This read-only field is reserved and always has the value 0.0Bit16Extended Address Bit 16This bit is the most significant bit of the 17-bit core address.28.3.13 Debug Control Register (DBG_C)Address: 18C0h base + Ch offset = 18CChBit 7 6 5 4 3 2 1 0Read DBGEN ARM TAG BRKEN 0 LOOP1WriteReset 1 1 0 0 0 0 0 0Chapter 28 Debug module (DBG)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 561
