4.3.1.1 Configuration optionsThe IRQ input enable control bit (IRQSC[IRQPE]) must be 1 for the IRQ signal to act asthe IRQ input. The user can choose the polarity of edges or levels detected (IRQEDG),whether the pin detects edges-only or edges and levels (IRQMOD), or whether an eventcauses an interrupt or only sets the IRQF flag, which can be polled by software.Since IRQ signal is from XBAR_OUT15, it is recommend XBAR_OUT15 is set to logichigh after reset.BIH and BIL instructions may be used to detect the level on the IRQ signal when IRQ isenabled.4.3.1.2 Edge and level sensitivityThe IRQSC[IRQMOD] control bit reconfigures the detection logic so that it can detectedge events and levels. In this detection mode, the IRQF status flag is set when an edge isdetected, if the IRQ signal changes from the de-asserted to the asserted level, but the flagis continuously set and cannot be cleared as long as the IRQ signal remains at the assertedlevel.IRQ Memory Map and Register DescriptionsIRQ memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page7F Interrupt Pin Request Status and Control Register (IRQ_SC) 8 R/W 00h 4.4.1/634.4.1 Interrupt Pin Request Status and Control Register (IRQ_SC)This direct page register includes status and control bits, which are used to configure theIRQ function, report status, and acknowledge IRQ events.Address: 7Fh base + 0h offset = 7FhBit 7 6 5 4 3 2 1 0Read 0 IRQPDD IRQEDG IRQPE IRQF 0 IRQIE IRQMODWrite IRQACKReset 0 0 0 0 0 0 0 04.4Chapter 4 InterruptMC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 63
