26.3.2.1 Alignment and compare output polarityThe edge-align (EDG) bit in the configure (CNFG) register selects either center-alignedor edge-aligned PWM generator outputs.PWM compare output polarity is selected by the CINVn bit field in the compare invert(CINV) register. Please see the output operations in the following two figures.The PWM compare output is driven to high state when the value of PWM value(VAL0-5) register is greater than the value of PWM counter, and PWM compare iscounting downwards if the corresponding channel CINVx=0. Or, the PWM compareoutput is driven to low state if the corresponding channel CINVx=1.The PWM compare output is driven to low state when the value of PWM value(VAL0-5) register matches the value of PWM counter, and PWM counter is countingupwards if the corresponding channel CINVx=0. Or, the PWM compare output is drivento high state if the corresponding channel CINVx=1.Up/Down CounterModulus = 4Alignment ReferencePWM Compare OutputDuty Cycle = 50%CINVx= 0CINVx = 1Figure 26-3. Center-Aligned PWM outputUp CounterModulus = 4Alignment ReferencePWM Compare OutputDuty Cycle = 50% CINVx = 0CINVx = 1Figure 26-4. Edge-Aligned PWM outputNOTEBecause of the equals-comparator architecture of this PWM, themodulus=0 case is considered illegal. However, the deadtimeconstraints and fault conditions will still be guaranteed.Functional descriptionMC9S08SU16 Reference Manual, Rev. 5, 4/2017486 NXP Semiconductors
