PDB_CTRL0 field descriptions (continued)Field Description0 Output is asserted and de-asserted by input trigger or counter rollover.1 Output a true high pulse.4MOD1PDB1 Counter Mode Enable0 Module is in single shot delay mode.1 Module is in continuous count mode.3TCF0PDB0 Timer Compare FlagThis bit is set when a successful compare occurs. Clear this bit by writing one to it.2TCIE0PDB0 Timer Compare Interrupt Enable0 Timer compare interrupt requests disabled.1 Timer compare interrupt requests enabled.1TRGOUT0PDB0 Trigger OutputConfigure PDB0 trigger output as an pulse or level when a successful compare occurs.0 Logic output mode, output is asserted and de-asserted by input trigger or counter rollover.1 Pulse output mode, output a true high pulse.0MOD0PDB0 Counter Mode Enable0 Module is in single shot delay mode.1 Module is in continuous count mode.23.6.2 PDB Control Register 1 (PDB_CTRL1)NOTESWCLR0 and SWCLR1 are also used as PDB status bits toindicate whether PDB0 and PDB1 are enabled or not.Do NOT use BSET and BCLR instruction to this register,which may cause unexpected software clear to SWCLR0 andSWCLR1.Address: 60h base + 1h offset = 61hBit 7 6 5 4 3 2 1 0Read CNTSEL1 CNTSEL0 PRESCALER SWCLR1 SWTRG1 SWCLR0 SWTRG0WriteReset 0 0 0 0 0 0 0 0Memory Map and Register DescriptionsMC9S08SU16 Reference Manual, Rev. 5, 4/2017426 NXP Semiconductors
