NOTEAfter I2C address matching wake-up, the master must wait atime long enough for the slave ISR to finish running and resendstart or repeat start signals.For the SRW bit to function properly, it only supports Address+Write to wake up by I2C address matching. Before enteringthe next low power mode, Address+Write must be sent tochange the SRW status.21.5.8 Double buffering modeIn the double buffering mode, the data transfer is processed byte by byte. However, thedata can be transferred without waiting for the interrupt or the polling to finish. Thismeans the write/read I2C_D operation will not block the data transfer, as the hardwarehas already finished the internal write or read. The benefit is that the baud rate is able toachieve higher speed.There are several items to consider as follows:• When initiating a double buffering transfer at Tx side, the user can write 2 values tothe I2C_D buffer before transfer. However, that is allowed only at one time perpackage frame (due to the buffer depth, and because two-times writes in each ISR arenot allowed). The second write to the I2C_D buffer must wait for the Empty flag. Onthe other hand, at Rx side the user can read twice in a one-byte transfer (if needed).NOTECheck Empty flag before write to I2C_D.Write twice to the I2C_D buffer ONLY after the addressmatching byte. Do not write twice (Address+Data) beforeSTART or at the beginning of I2C transfer, especially whenthe baud rate is very slow.• To write twice in one frame, during the next-to-last ISR, do a dummy read from theI2C_D buffer at Tx side (or the TCF will stay high, because the TCF is cleared bywrite/read operation). In the next-to-last ISR, do not send data again (the buffer datawill be under running).• To keep new ISRs software-compatible with previous ISRs, the write/read I2C_Doperation will not block the internal-hardware-released SCL/SDA signals. At theFunctional descriptionMC9S08SU16 Reference Manual, Rev. 5, 4/2017390 NXP Semiconductors
