Chapter 9System Integration Module (SIM)9.1 Chip specific windowed COPThe windowed COP (WCOP) module triggers a system reset if it is allowed to time out.The program is expected to periodically reload the COP timer, thereby preventing it fromtiming out. However, if a fault occurs that causes the program to stop working, the timerwill not be reloaded and it will time out. The resulting trigger of a system reset brings thesystem back from an unresponsive state into a normal state.After any reset, the WCOP is enabled. If the WCOP is not used in an application, it canbe disabled by clearing SIM_SOPT1[COPT].The WCOP counter is reset by writing 0x55 and 0xAA (in that order) to the address ofthe SIM_SRS during the selected timeout period. Writes do not affect the data in thatfield. As soon as the write sequence is complete, the WCOP timeout period is restarted. Ifthe program fails to perform this restart during the timeout period, the microcontrollerresets. Also, if any value other than 0x55 or 0xAA is written to the SIM_SRS register, themicrocontroller immediately resets.Windowed watchdog operation is available by setting SIM_SOPT1[COPW], In thismode, writes to service watchdog register SIM_SRS to clear WCOP counter must be in aselected timeout period. A premature write immediately resets the chip.WCOP has four clock selections: BUSCLK (20 MHz), ICSIRCLK (up to the 32 kHz)and an independent clock source LPOCLK (up to the 20 kHz), CLKINCustomization:• Primary clock: BUSCLK (20 MHz)• Input clock option: BUSCLK (20 MHz); ICSIRCLK (up to the 32 kHz), LPOCLK(up to the 20 kHz), CLKIN (40 MHz)• WCOP is a part of SIM. Its register set is a subset of SIM registers.Module Instances:• OneMC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 97
