DBG_C field descriptionsField Description7DBGENDBG Module Enable BitThe DBGEN bit enables the DBG module. The DBGEN bit is forced to zero and cannot be set if the MCUis secure.0 DBG not enabled.1 DBG enabled.6ARMArm BitThe ARM bit controls whether the debugger is comparing and storing data in FIFO.0 Debugger not armed.1 Debugger armed.5TAGTag or Force BitThe TAG bit controls whether a debugger or comparator C breakpoint will be requested as a tag or forcebreakpoint to the CPU. The TAG bit is not used if BRKEN = 0.0 Force request selected.1 Tag request selected.4BRKENBreak Enable BitThe BRKEN bit controls whether the debugger will request a breakpoint to the CPU at the end of a tracerun, and whether comparator C will request a breakpoint to the CPU.0 CPU break request not enabled.1 CPU break request enabled.3–1ReservedThis field is reserved.This read-only field is reserved and always has the value 0.0LOOP1Select LOOP1 Capture ModeThis bit selects either normal capture mode or LOOP1 capture mode. LOOP1 is not used in event-onlymodes.0 Normal operation - capture COF events into the capture buffer FIFO.1 LOOP1 capture mode enabled. When the conditions are met to store a COF value into the FIFO,compare the current COF address with the address in comparator C. If these addresses match,override the FIFO capture and do not increment the FIFO count. If the address does not matchcomparator C, capture the COF address, including the PPACC indicator, into the FIFO and intocomparator C..28.3.14 Debug Trigger Register (DBG_T)NOTEThe figure shows the values in POR or non-end-run reset. Allthe bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the ARM andBRKEN bits are cleared but the remaining control bits in thisregister do not change after reset.Memory map and registersMC9S08SU16 Reference Manual, Rev. 5, 4/2017562 NXP Semiconductors
