6.2.2 Wait modeWait mode is entered by executing a WAIT instruction. Upon execution of the WAITinstruction, the CPU enters a low-power state in which it is not clocked. The CCR [I] iscleared when the CPU enters the wait mode, enabling interrupts. When an interruptrequest occurs, the CPU exits the wait mode and resumes processing, beginning with thestacking operations leading to the interrupt service routine.While the MCU is in wait mode, there are some restrictions on which background debugcommands can be used. Only the BACKGROUND command and memory-access-with-status commands are available when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that theMCU is in either stop or wait mode. The BACKGROUND command can be used towake the MCU from wait mode and enter active background mode.6.2.3 Stop modeTo enter stop, the user must execute a STOP instruction with stop mode enabled(SIM_SOPT1[STOPE] = 1). The ICS enters its standby state, as does the voltageregulator and the ADC. The states of all of the internal registers and logic, as well as theRAM content, are maintained. The I/O pin states are not latched at the pin. Instead theyare maintained by virtue of the states of the internal logic driving the pins beingmaintained.Exit from stop is done by asserting reset or through an interrupt. The interrupt include theasynchronous interrupt from the IRQ or KBI pins or ADC, CMP, I2C, SCI.If stop is exited by means of the RESET pin, then the MCU will be reset and operationwill resume after taking the reset vector. Exit by means of an asynchronous interrupt orthe real-time interrupt will result in the MCU taking the appropriate interrupt vector.Both low voltage detection and low reset are disabled in stop mode.6.2.4 Active BDM enabled in stop modeEntry into the active background mode from run mode is enabled if theBDC_SCR[ENBDM] bit is set. This register is described in the development support. IfBDC_SCR[ENBDM] is set when the CPU executes a STOP instruction, the systemFeaturesMC9S08SU16 Reference Manual, Rev. 5, 4/201772 NXP Semiconductors
