9.8.6 System Options Register 2 (SIM_SOPT2)This register may be read and written at any time.Address: 1800h base + 5h offset = 1805hBit 7 6 5 4 3 2 1 0Read ESFC WPXB 0 BUSREFWriteReset 0 0 0 0 0 0 0 0SIM_SOPT2 field descriptionsField Description7ESFCEnable Stalling Flash ControllerEnables stalling flash controller when flash is busy. When software needs to access the flash memorywhile a flash memory resource is being manipulated by a flash command, software can enable a stallmechanism to avoid a read collision. The stall mechanism allows software to execute code from the sameblock on which flash operations are being performed. However, software must ensure the sector the flashoperations are being performed on is not the same sector from which the code is executing. ESFCenables the stall mechanism. This bit must be set only just before the flash operation is executed andmust be cleared when the operation completes.0 Disable stalling flash controller when flash is busy.1 Enable stalling flash controller when flash is busy.6WPXBWrite Protection for XBAR registersThis field configures the write-protection for XBAR registers0 XBAR registers are writable.1 XBAR registers are not writable.5–3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.BUSREF BUS Output selectThis bit enables bus clock output on PTB7 via an optional prescalar.000 Bus.001 Bus divided by 2.010 Bus divided by 4.011 Bus divided by 8.100 Bus divided by 16.101 Bus divided by 32.110 Bus divided by 64.111 Bus divided by 128.Memory map and register definitionMC9S08SU16 Reference Manual, Rev. 5, 4/2017110 NXP Semiconductors
