26.4.15 PWM Deadtime Register: Low (PWM_DTIMnL)Deadtime operation is only applicable to complementary channel operation. The 12-bitvalue written to this write-protected registers is in terms of PWM clock cycles. Reset setsthe PWM deadtime register to a default value of 0x0FFF, selecting a deadtime of 4096-PWM clock cycles minus one PWM clock cycle. This register is write protected after theWP bit in the PWM configuration register is set. Reserved bits 15–12 cannot be modified.They are read as zero.NOTEDeadtime is affected by changes to the prescaler value. Thedeadtime duration is determined as follows: DT = P × PWMDT– 1, where DT is deadtime, P is the prescaler value, PWMDT isthe programmed value of dead time. For example: if theprescaler is programmed for a divide-by-two and PWMDT isset to five, then P = 2 and the deadtime value is equal to DT = 2× 5 – 1 = 9 PWM clock cycles. A special case exists when the P= 1, DT = PWMDTThe PWMDT field is used to control the deadtime during transitions of the even PWMoutput.Address: 40h base + 18h offset + (2d × i), where i=0d to 1dBit 7 6 5 4 3 2 1 0Read PWMDT7_0WriteReset 1 1 1 1 1 1 1 1PWM_DTIMnL field descriptionsField DescriptionPWMDT7_0 PWM Pulse Width Value7:026.4.16 PWM Deadtime Register: High (PWM_DTIMnH)Deadtime operation is only applicable to complementary channel operation. The 12-bitvalue written to this write-protected registers is in terms of PWM clock cycles. Reset setsthe PWM deadtime register to a default value of 0x0FFF, selecting a deadtime of 4096-PWM clock cycles minus one PWM clock cycle. This register is write protected after theWP bit in the PWM configuration register is set. Reserved bits 15–12 cannot be modified.They are read as zero.Memory Map and Register DescriptionsMC9S08SU16 Reference Manual, Rev. 5, 4/2017518 NXP Semiconductors
