/* the following code segment demonstrates setting the ICS to FBI mode using the factorytrim value. The resulting ICSOUT frequency is fint_ft/BDIV. Note that the FLL will berunning at a frequency of fint_ft*1024/BDIV even though the FLL is bypassed. */ICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configuredICS_C1 = 0x44; // internal reference clock as source for ICSOUTwhile ((ICS_S & 0x0C) != 0x04); // wait until internal reference is selectedICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies12.5.3 Initializing FEE modeThe following code segment demonstrates setting ICS to FEE mode.Example: 12.5.3.1 FEE mode initialization routine/* the following code segment demonstrates setting the ICS to FEE mode generating a 32MHZbus clock frequency using an external 8MHz crystal */SIM_SOPT1[RANGE] = 1; // high rangeICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configuredICS_C1 = 0x18; // 8MHz external reference clock/256 as source to FLLwhile ((ICS_S & ICS_S_IREFST_MASK) == 1); // wait for external source selectedwhile ((ICS_S & ICS_S_LOCK_MASK) == 0); // wait for FLL to lockICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequencies12.5.4 Initializing FBE modeThe following code segment demonstrates setting ICS to FBE mode.Example: 12.5.4.1 FBE mode initialization routine/* the following code segment demonstrates setting the ICS to FBE mode generating 20MHZ coreclock frequency using an external 20MHz crystal */SIM_SOPT1[RANGE] = 1; // high rangeICS_C2 = 0x20; // BDIV=divide by 2 – use default until clock dividers configuredICS_C1 = 0xA0; // 20MHz external clock as ICSOUT source; FLL source = 20MHz/512while ((ICS_S & ICS_S_IREFST_MASK) == 1); // wait for external source selectedwhile ((ICS_S & 0x0C) != 0x08); // wait until FBE mode is selectedICS_C2 = 0x00; // BDIV=divide by 1 – allows max core and bus clock frequenciesChapter 12 Internal Clock Source (ICS)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 203
