SCIx_BDH field descriptions (continued)Field DescriptionThe 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCIbaud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supplycurrent. When BR is 1 - 8191, the SCI baud rate equals BUSCLK/(16×BR).22.4.2 SCI Baud Rate Register: Low (SCIx_BDL)This register, along with SCI_BDH, control the prescale divisor for SCI baud rategeneration. To update the 13-bit baud rate setting [SBR12:SBR0], first write toSCI_BDH to buffer the high half of the new value and then write to SCI_BDL. Theworking value in SCI_BDH does not change until SCI_BDL is written.SCI_BDL is reset to a non-zero value, so after reset the baud rate generator remainsdisabled until the first time the receiver or transmitter is enabled; that is, SCI_C2[RE] orSCI_C2[TE] bits are written to 1.Address: 1868h base + 1h offset = 1869hBit 7 6 5 4 3 2 1 0Read SBRWriteReset 0 0 0 0 0 1 0 0SCIx_BDL field descriptionsField DescriptionSBR Baud Rate Modulo DivisorThese 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the SCIbaud rate generator. When BR is cleared, the SCI baud rate generator is disabled to reduce supplycurrent. When BR is 1 - 8191, the SCI baud rate equals BUSCLK/(16×BR).22.4.3 SCI Control Register 1 (SCIx_C1)This read/write register controls various optional features of the SCI system.Address: 1868h base + 2h offset = 186AhBit 7 6 5 4 3 2 1 0Read LOOPS SCISWAI RSRC M WAKE ILT PE PTWriteReset 0 0 0 0 0 0 0 0Chapter 22 Serial Communications Interface (SCI)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 401
