18.10.6 MUX Control Register (CMP_MUXCR)NOTEPEN and MEN bits should be enabled or disabled together withCR1[EN] bit.Address: 68h base + 5h offset = 6DhBit 7 6 5 4 3 2 1 0Read 0 PSEL 0 MSELWriteReset 0 0 0 0 0 0 0 0CMP_MUXCR field descriptionsField Description7–6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.5–4PSELPlus Input MUX ControlDetermines which input is selected for the plus input of the comparator. For INx inputs, refer to CMP, DACand ANMUX Blocks Diagram.NOTE: When an inappropriate operation selects the same input for both MUXes, the comparatorautomatically shuts down to prevent itself from becoming a noise generator.00 IN001 IN110 IN211 6-bit DAC output is selected3–2ReservedThis field is reserved.This read-only field is reserved and always has the value 0.MSEL Minus Input MUX ControlDetermines which input is selected for the minus input of the comparator. For INx inputs, refer to CMP,DAC and ANMUX Blocks Diagram.NOTE: When an inappropriate operation selects the same input for both MUXes, the comparatorautomatically shuts down to prevent itself from becoming a noise generator.00 IN001 IN110 IN211 6-bit DAC output is selectedMemory Map/Register DefinitionsMC9S08SU16 Reference Manual, Rev. 5, 4/2017300 NXP Semiconductors
