PWM_CTRLH field descriptions (continued)Field Description0010 Every 3 PWM opportunities0011 Every 4 PWM opportunities0100 Every 5 PWM opportunity0101 Every 6 PWM opportunities0110 Every 7 PWM opportunities0111 Every 8 PWM opportunities1000 Every 9 PWM opportunity1001 Every 10 PWM opportunities1010 Every 11 PWM opportunities1011 Every 12 PWM opportunities1100 Every 13 PWM opportunity1101 Every 14 PWM opportunities1110 Every 15 PWM opportunities1111 Every 16 PWM opportunities3HALFHalf Cycle ReloadThis read/write bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect on edge-aligned PWMs.0 Half-cycle reloads disabled.1 Half-cycle reloads enabled.Reserved This field is reserved.This read-only field is reserved and always has the value 0.26.4.3 PWM Fault Control Register: Low (PWM_FCTRLL)Address: 40h base + 2h offset = 42hBit 7 6 5 4 3 2 1 0Read FIE3 FMODE3 FIE2 FMODE2 FIE1 FMODE1 FIE0 FMODE0WriteReset 0 0 0 0 0 0 0 0PWM_FCTRLL field descriptionsField Description7FIE3FAULT3 Pin Interrupt EnableThis read/write bit enables interrupt requests generated by the filtered FAULT3 pin. A reset clears FIE3.NOTE: The fault protection circuit is independent of the FIE3 bits and is always active. If a fault isdetected, the PWM pins are disabled according to the PWM disable mapping register.0 FAULT3 interrupt requests disabled1 FAULT3 interrupt requests enabled6FMODE3FAULT3 Pin Clearing ModeThis read/write bit selects automatic or manual clearing of FAULT3 pin faults. A reset clears FMODE3.Table continues on the next page...Memory Map and Register DescriptionsMC9S08SU16 Reference Manual, Rev. 5, 4/2017508 NXP Semiconductors
