Table 11-38. Set factory margin level command error handlingRegister Error bit Error conditionFSTATACCERRSet if CCOBIX[2:0] != 010 at command launchSet if command is not available in current mode (see Table 11-4)Set if an invalid global address [23:0] is suppliedSet if an invalid margin level setting is suppliedFPVIOL NoneMGSTAT1 NoneMGSTAT0 NoneCAUTIONFactory margin levels must only be used during verify of theinitial factory programming.NoteFactory margin levels can be used to check that Flash memorycontents have adequate margin for data retention at the normallevel setting. If unexpected results are encountered whenchecking flash memory contents at factory margin levels, thefash memory contents must be erased and reprogrammed.11.4 Memory map and register definitionThis section presents a high-level summary of the registers and how they are mapped.The registers can be accessed in 32-bits, 16-bits (aligned on data[31:16] or on data[15:0])or 8-bits. In the case of the writable registers, the write accesses are forbidden duringflash command execution. For more details, see Caution note in Flash memory map.FTMRH memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page1830 Flash Clock Divider Register (FTMRH_FCLKDIV) 8 R/W 00h 11.4.1/1811831 Flash Security Register (FTMRH_FSEC) 8 R Undefined 11.4.2/1821832 Flash CCOB Index Register (FTMRH_FCCOBIX) 8 R/W 00h 11.4.3/1831834 Flash Configuration Register (FTMRH_FCNFG) 8 R/W 00h 11.4.4/1831836 Flash Status Register (FTMRH_FSTAT) 8 R/W 80h 11.4.5/1841838 Flash Protection Register (FTMRH_FPROT) 8 R See section 11.4.6/185183A Flash Common Command Object Register:High(FTMRH_FCCOBHI) 8 R/W 00h 11.4.7/186Table continues on the next page...Memory map and register definitionMC9S08SU16 Reference Manual, Rev. 5, 4/2017180 NXP Semiconductors
