Table 17-5. Total conversion time vs. control conditions (continued)Conversion type ADICLK ADLSMP Max total conversion timeSingle or first continuous 8-bit 11 1 5 μs + 40 ADCK + 5 bus clock cyclesSingle or first continuous 10-bit or 12-bit 11 1 5 μs + 43 ADCK + 5 bus clock cyclesSubsequent continuous 8-bit;fBUS > fADCKxx 0 17 ADCK cyclesSubsequent continuous 10-bit or 12-bit;fBUS > fADCKxx 0 20 ADCK cyclesSubsequent continuous 8-bit;fBUS > fADCK/11xx 1 37 ADCK cyclesSubsequent continuous 10-bit or 12-bit;fBUS > fADCK/11xx 1 40 ADCK cyclesThe maximum total conversion time is determined by the selected clock source and thedivide ratio. The clock source is selectable by the ADC_SC3[ADICLK] bits, and thedivide ratio is specified by the ADC_SC3[ADIV] bits. For example, in 10-bit mode, withthe bus clock selected as the input clock source, the input clock divide-by-1 ratioselected, and a bus frequency of 8 MHz, then the conversion time for a single conversionas given below:The number of bus cycles at 8 MHz is:NoteThe ADCK frequency must be between fADCK minimum andfADCK maximum to meet ADC specifications.17.5.4 Automatic compare functionThe compare function can be configured to check for an upper or lower limit. After theinput is sampled and converted, the result is added to the complement of the comparevalue (ADC_CV). When comparing to an upper limit (ADC_SC2[ACFGT] = 1), if theresult is greater-than or equal-to the compare value, ADC_SC1[COCO] is set. Whencomparing to a lower limit (ADC_SC2[ACFGT] = 0), if the result is less than thecompare value, ADC_SC1[COCO] is set. The value generated by the addition of theconversion result and the complement of the compare value is transferred to ADC_R.Functional descriptionMC9S08SU16 Reference Manual, Rev. 5, 4/2017274 NXP Semiconductors
