MTIM_CLK field descriptions (continued)Field Description5–4CLKSClock source selectThese two read/write bits select one of four different clock sources as the input to the MTIM16 prescaler.Changing the clock source while the counter is active does not clear the counter. The count continues withthe new clock source. Reset clears CLKS to 00.00 Encoding 0. Bus clock (BUSCLK)01 Encoding 1. Fixed-frequency clock (XCLK)10 Encoding 3. External source (TCLK pin), falling edge11 Encoding 4. External source (TCLK pin), rising edgePS Clock source prescalerThese four read/write bits select one of nine outputs from the 8-bit prescaler. Changing the prescaler valuewhile the counter is active does not clear the counter. The count continues with the new prescaler value.Reset clears PS to 0000.0000 Encoding 0. MTIM16 clock source / 10001 Encoding 1. MTIM16 clock source / 20010 Encoding 2. MTIM16 clock source / 40011 Encoding 3. MTIM16 clock source / 80100 Encoding 4. MTIM16 clock source / 160101 Encoding 5. MTIM16 clock source / 320110 Encoding 6. MTIM16 clock source / 640111 Encoding 7. MTIM16 clock source / 1281xxx Encoding 8+. MTIM16 clock source / 25613.5.3 MTIM16 counter register high (MTIM_CNTH)This register is the read-only value of the high byte of the current MTIM16 16-bitcounter.When either the CNTH or CNTL register is read, the content of the two registers islatched into a buffer where they remain latched until the other register is read. Thisallows the coherent 16-bit value to be read in both big-endian and little-endian compileenvironments and ensures the 16-bit counter is unaffected by the read operation. Thecoherency mechanism is automatically restarted by an MCU reset or by setting the TRSTbit of the SC register (whether BDM mode is active or not).When BDM is active, the coherency mechanism is frozen such that the buffer latchesremain in the state they were in when BDM became active, even if one or both halves ofthe counter register are read while BDM is active. This assures that if the user was in themiddle of reading a 16-bit register when BDM became active, the appropriate value fromthe other half of the 16-bit value is read after returning to normal execution. The valueread from the CNTH and CNTL registers in BDM mode is the value of these registersand not the value of their read buffer.Chapter 13 Modulo Timer (MTIM)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 211
