PORT_PTAD field descriptionsField DescriptionPTAD Port A Data Register BitsFor port A pins that are configured as inputs, a read returns the logic level on the pin.For port A pins that are configured as outputs, a read returns the last value that was written to this register.Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic levelis driven out of the corresponding MCU pin.8.5.2 Port B Data Register (PORT_PTBD)Reading and writing of parallel I/O is accomplished through this register.When a digital peripheral module or system function is selected and enabled on a pin,reads of this register still returns the pin value of the associated pin if PORT_PTBDD[n]= 0 (n=1-7). When a shared analog function is selected for a pin, all digital pin functionsare disabled. A read of this register returns a value of 0 for any bits that have sharedanalog functions enabled.A write of valid data to this register must occur before setting the direction control bit ofan associated port pin. This ensures that the pin will not be driven with an incorrect datavalue.Address: 0h base + 1h offset = 1hBit 7 6 5 4 3 2 1 0Read PTBDWriteReset 0 0 0 0 0 0 0 0PORT_PTBD field descriptionsField DescriptionPTBD Port B Data Register BitsFor port B pins that are configured as inputs, a read returns the logic level on the pin.For port B pins that are configured as outputs, a read returns the last value that was written to this register.Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic levelis driven out of the corresponding MCU pin.8.5.3 Port C Data Register (PORT_PTCD)Reading and writing of parallel I/O is accomplished through this register.Chapter 8 Port Control (PORT)MC9S08SU16 Reference Manual, Rev. 5, 4/2017NXP Semiconductors 87
