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NXP Semiconductors MKL25Z128VFT4 manuals

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MKL25Z128VFT4

Table of contents
  1. Table Of Contents
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  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Overview
  32. Typographic notation
  33. KL25 Sub-Family Introduction
  34. Module functional categories
  35. ARM® Cortex™-M0+ Core Modules
  36. Memories and Memory Interfaces
  37. Security and Integrity modules
  38. Communication interfaces
  39. Human-machine interfaces
  40. Introduction
  41. KL25 Sub-Family Reference Manual, Rev. 3, September
  42. Analog reference options
  43. Nested Vectored Interrupt Controller (NVIC) Configuration
  44. Asynchronous wake-up interrupt controller (AWIC) configuration
  45. System Modules
  46. System Mode Controller (SMC) Configuration
  47. Low-Leakage Wake-up Unit (LLWU) Configuration
  48. MCM Configuration
  49. Crossbar-Light Switch Configuration
  50. Peripheral Bridge Configuration
  51. DMA request multiplexer configuration
  52. DMA Controller Configuration
  53. Computer Operating Properly (COP) Watchdog Configuration
  54. Clock Modules
  55. OSC Configuration
  56. Flash Memory Controller Configuration
  57. Analog
  58. CMP Configuration
  59. bit DAC Configuration
  60. Timers
  61. PIT Configuration
  62. Low-power timer configuration
  63. RTC configuration
  64. SPI configuration
  65. I2C Configuration
  66. UART Configuration
  67. Human-machine interfaces (HMI)
  68. TSI Configuration
  69. Memory Map
  70. Flash Memory Map
  71. Alternate Non-Volatile IRC User Trim Description
  72. Peripheral bridge (AIPS-Lite) memory map
  73. Modules Restricted Access in User Mode
  74. Clock definitions
  75. Device clock summary
  76. Internal clocking requirements
  77. VLPR mode clocking
  78. Clock Gating
  79. PMC 1-kHz LPO clock
  80. RTC clocking
  81. TPM clocking
  82. UART clocking
  83. Power-on reset (POR)
  84. MCU Resets
  85. Reset Pin
  86. Boot sequence
  87. DMA Wakeup
  88. Compute Operation
  89. Peripheral Doze
  90. Entering and exiting power modes
  91. Security Interactions with Debug
  92. SWD status and control registers
  93. MDM-AP Control Register
  94. MDM-AP Status Register
  95. Micro Trace Buffer (MTB)
  96. Port control and interrupt module features
  97. KL25 Pinouts
  98. Module Signal Description Tables
  99. Core Modules
  100. Detailed signal description
  101. Pin Control Register n (PORTx_PCRn)
  102. Global Pin Control Low Register (PORTx_GPCLR)
  103. Global Pin Control High Register (PORTx_GPCHR)
  104. Functional description
  105. Global pin control
  106. System Options Register 1 (SIM_SOPT1)
  107. SOPT1 Configuration Register (SIM_SOPT1CFG)
  108. System Options Register 2 (SIM_SOPT2)
  109. System Options Register 4 (SIM_SOPT4)
  110. System Options Register 5 (SIM_SOPT5)
  111. System Options Register 7 (SIM_SOPT7)
  112. System Device Identification Register (SIM_SDID)
  113. System Clock Gating Control Register 4 (SIM_SCGC4)
  114. System Clock Gating Control Register 5 (SIM_SCGC5)
  115. System Clock Gating Control Register 6 (SIM_SCGC6)
  116. System Clock Gating Control Register 7 (SIM_SCGC7)
  117. System Clock Divider Register 1 (SIM_CLKDIV1)
  118. Flash Configuration Register 2 (SIM_FCFG2)
  119. Unique Identification Register Mid Low (SIM_UIDML)
  120. COP Control Register (SIM_COPC)
  121. Service COP Register (SIM_SRVCOP)
  122. Memory map and register descriptions
  123. Power Mode Control register (SMC_PMCTRL)
  124. Stop Control Register (SMC_STOPCTRL)
  125. Power Mode Status register (SMC_PMSTAT)
  126. Power mode entry/exit sequencing
  127. Run modes
  128. Wait modes
  129. Stop modes
  130. Debug in low power modes
  131. I/O retention
  132. Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)
  133. Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)
  134. Regulator Status And Control register (PMC_REGSC)
  135. Modes of operation
  136. Block diagram
  137. LLWU signal descriptions
  138. LLWU Pin Enable 1 register (LLWU_PE1)
  139. LLWU Pin Enable 2 register (LLWU_PE2)
  140. LLWU Pin Enable 3 register (LLWU_PE3)
  141. LLWU Pin Enable 4 register (LLWU_PE4)
  142. LLWU Module Enable register (LLWU_ME)
  143. LLWU Flag 1 register (LLWU_F1)
  144. LLWU Flag 2 register (LLWU_F2)
  145. LLWU Flag 3 register (LLWU_F3)
  146. LLWU Pin Filter 1 register (LLWU_FILT1)
  147. LLWU Pin Filter 2 register (LLWU_FILT2)
  148. LLS mode
  149. System Reset Status Register 1 (RCM_SRS1)
  150. Reset Pin Filter Control register (RCM_RPFC)
  151. Reset Pin Filter Width register (RCM_RPFW)
  152. Memory Map and Register Definition
  153. Additional Details on Decorated Addresses and GPIO Accesses
  154. Application Information
  155. Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
  156. Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
  157. Compute Operation Control Register (MCM_CPO)
  158. Features
  159. MTB_DWT Memory Map
  160. Arbitration
  161. Initialization/application information
  162. General operation
  163. External signal description
  164. DMA channels with periodic triggering capability
  165. Freescale Semiconductor, Inc
  166. DMA channels with no triggering capability
  167. DMA Transfer Overview
  168. Memory Map and Registers
  169. Source Address Register (DMA_SARn)
  170. Destination Address Register (DMA_DARn)
  171. DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
  172. DMA Control Register (DMA_DCRn)
  173. Dual-Address Data Transfer Mode
  174. Advanced Data Transfer Controls: Auto-Alignment
  175. Termination
  176. MCG Control 1 Register (MCG_C1)
  177. MCG Control 2 Register (MCG_C2)
  178. MCG Control 3 Register (MCG_C3)
  179. MCG Control 5 Register (MCG_C5)
  180. MCG Control 6 Register (MCG_C6)
  181. MCG Status Register (MCG_S)
  182. MCG Status and Control Register (MCG_SC)
  183. MCG Auto Trim Compare Value High Register (MCG_ATCVH)
  184. MCG Control 7 Register (MCG_C7)
  185. MCG Control 9 Register (MCG_C9)
  186. Low Power Bit Usage
  187. MCG PLL clock
  188. Initialization / Application information
  189. Using a 32.768 kHz reference
  190. External Crystal / Resonator Connections
  191. External Clock Connections
  192. Memory Map/Register Definitions
  193. OSC Module Modes
  194. Counter
  195. Reset
  196. Glossary
  197. Flash Configuration Field Description
  198. Register Descriptions
  199. Flash Protection
  200. Flash Operation in Low-Power Modes
  201. Flash Reads and Ignored Writes
  202. Margin Read Commands
  203. Flash Command Description
  204. Security
  205. Reset Sequence
  206. ADC Signal Descriptions
  207. Voltage Reference Select
  208. Analog Channel Inputs (ADx)
  209. ADC Status and Control Registers 1 (ADCx_SC1n)
  210. ADC Configuration Register 1 (ADCx_CFG1)
  211. ADC Configuration Register 2 (ADCx_CFG2)
  212. ADC Data Result Register (ADCx_Rn)
  213. Compare Value Registers (ADCx_CVn)
  214. Status and Control Register 2 (ADCx_SC2)
  215. Status and Control Register 3 (ADCx_SC3)
  216. ADC Offset Correction Register (ADCx_OFS)
  217. ADC Minus-Side Gain Register (ADCx_MG)
  218. ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
  219. ADC Plus-Side General Calibration Value Register (ADCx_CLP1)
  220. ADC Minus-Side General Calibration Value Register (ADCx_CLMD)
  221. ADC Minus-Side General Calibration Value Register (ADCx_CLM4)
  222. ADC Minus-Side General Calibration Value Register (ADCx_CLM2)
  223. ADC Minus-Side General Calibration Value Register (ADCx_CLM0)
  224. Clock select and divide control
  225. Voltage reference selection
  226. Conversion control
  227. Automatic compare function
  228. Calibration function
  229. User-defined offset function
  230. Temperature sensor
  231. MCU Normal Stop mode operation
  232. MCU Low-Power Stop mode operation
  233. Sources of error
  234. bit DAC key features
  235. ANMUX key features
  236. CMP block diagram
  237. CMP Control Register 1 (CMPx_CR1)
  238. CMP Filter Period Register (CMPx_FPR)
  239. DAC Control Register (CMPx_DACCR)
  240. MUX Control Register (CMPx_MUXCR)
  241. Power modes
  242. Startup and operation
  243. Low-pass filter
  244. CMP interrupts
  245. CMP Asyncrhonous DMA support
  246. DAC interrupts
  247. Memory map/register definition
  248. DAC Data High Register (DACx_DATnH)
  249. DAC Control Register (DACx_C0)
  250. DAC Control Register 1 (DACx_C1)
  251. DMA operation
  252. TPM_EXTCLK — TPM External Clock
  253. Status and Control (TPMx_SC)
  254. Counter (TPMx_CNT)
  255. Modulo (TPMx_MOD)
  256. Channel (n) Status and Control (TPMx_CnSC)
  257. Channel (n) Value (TPMx_CnV)
  258. Configuration (TPMx_CONF)
  259. Prescaler
  260. Input Capture Mode
  261. Output Compare Mode
  262. Edge-Aligned PWM (EPWM) Mode
  263. Center-Aligned PWM (CPWM) Mode
  264. Registers Updated from Write Buffers
  265. Reset Overview
  266. PIT Upper Lifetime Timer Register (PIT_LTMR64H)
  267. Timer Load Value Register (PIT_LDVALn)
  268. Timer Control Register (PIT_TCTRLn)
  269. Timer Flag Register (PIT_TFLGn)
  270. Interrupts
  271. Example configuration for chained timers
  272. Example configuration for the lifetime timer
  273. LPTMR signal descriptions
  274. Low Power Timer Control Status Register (LPTMRx_CSR)
  275. Low Power Timer Prescale Register (LPTMRx_PSR)
  276. Low Power Timer Compare Register (LPTMRx_CMR)
  277. LPTMR compare
  278. LPTMR hardware trigger
  279. RTC Signal Descriptions
  280. RTC Time Seconds Register (RTC_TSR)
  281. RTC Time Alarm Register (RTC_TAR)
  282. RTC Control Register (RTC_CR)
  283. RTC Status Register (RTC_SR)
  284. RTC Lock Register (RTC_LR)
  285. RTC Interrupt Enable Register (RTC_IER)
  286. Time counter
  287. Time alarm
  288. Update mode
  289. USB On-The-Go
  290. USB-FS Features
  291. Programmers interface
  292. RX vs. TX as a USB target device or USB host
  293. Addressing BDT entries
  294. USB transaction
  295. Peripheral ID register (USBx_PERID)
  296. Peripheral ID Complement register (USBx_IDCOMP)
  297. Peripheral Additional Info register (USBx_ADDINFO)
  298. OTG Interrupt Control Register (USBx_OTGICR)
  299. OTG Status register (USBx_OTGSTAT)
  300. OTG Control register (USBx_OTGCTL)
  301. Interrupt Status register (USBx_ISTAT)
  302. Interrupt Enable register (USBx_INTEN)
  303. Error Interrupt Status register (USBx_ERRSTAT)
  304. Error Interrupt Enable register (USBx_ERREN)
  305. Control register (USBx_CTL)
  306. Address register (USBx_ADDR)
  307. BDT Page Register 1 (USBx_BDTPAGE1)
  308. Frame Number Register High (USBx_FRMNUMH)
  309. SOF Threshold Register (USBx_SOFTHLD)
  310. BDT Page Register 2 (USBx_BDTPAGE2)
  311. USB Control register (USBx_USBCTRL)
  312. USB OTG Observe register (USBx_OBSERVE)
  313. USB OTG Control register (USBx_CONTROL)
  314. Frame Adjust Register (USBx_USBFRMADJUST)
  315. OTG and Host mode operation
  316. On-The-Go operation
  317. OTG dual role A device operation
  318. OTG dual role B device operation
  319. Block Diagrams
  320. SPSCK — SPI Serial Clock
  321. SPI control register 2 (SPIx_C2)
  322. SPI baud rate register (SPIx_BR)
  323. SPI status register (SPIx_S)
  324. SPI data register (SPIx_D)
  325. SPI match register (SPIx_M)
  326. Master Mode
  327. Slave Mode
  328. SPI Transmission by DMA
  329. SPI Clock Formats
  330. SPI Baud Rate Generation
  331. Special Features
  332. Error Conditions
  333. Pseudo-Code Example
  334. I2C Address Register 1 (I2Cx_A1)
  335. I2C Frequency Divider register (I2Cx_F)
  336. I2C Control Register 1 (I2Cx_C1)
  337. I2C Status register (I2Cx_S)
  338. I2C Data I/O register (I2Cx_D)
  339. I2C Control Register 2 (I2Cx_C2)
  340. I2C Programmable Input Glitch Filter register (I2Cx_FLT)
  341. I2C Range Address register (I2Cx_RA)
  342. I2C SMBus Control and Status register (I2Cx_SMB)
  343. I2C Address Register 2 (I2Cx_A2)
  344. bit address
  345. Address matching
  346. Resets
  347. Programmable input glitch filter
  348. Address matching wakeup
  349. DMA support
  350. Register definition
  351. UART Baud Rate Register High (UARTx_BDH)
  352. UART Baud Rate Register Low (UARTx_BDL)
  353. UART Control Register 2 (UARTx_C2)
  354. UART Status Register 1 (UARTx_S1)
  355. UART Status Register 2 (UARTx_S2)
  356. UART Control Register 3 (UARTx_C3)
  357. UART Data Register (UARTx_D)
  358. UART Match Address Registers 1 (UARTx_MA1)
  359. UART Match Address Registers 2 (UARTx_MA2)
  360. UART Control Register 5 (UARTx_C5)
  361. Receiver functional description
  362. Additional UART functions
  363. Interrupts and status flags
  364. UART Baud Rate Register: High (UARTx_BDH)
  365. UART Control Register 1 (UARTx_C1)
  366. Baud rate generation
  367. Port Data Output Register (GPIOx_PDOR)
  368. Port Set Output Register (GPIOx_PSOR)
  369. Port Toggle Output Register (GPIOx_PTOR)
  370. Port Data Direction Register (GPIOx_PDDR)
  371. Port Data Output Register (FGPIOx_PDOR)
  372. Port Set Output Register (FGPIOx_PSOR)
  373. Port Toggle Output Register (FGPIOx_PTOR)
  374. Port Data Direction Register (FGPIOx_PDDR)
  375. IOPORT
  376. TSI DATA Register (TSIx_DATA)
  377. TSI Threshold Register (TSIx_TSHD)
  378. Capacitance measurement
  379. TSI measurement result
  380. Scan times
  381. Current source
  382. Wake up MCU from low power modes
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