Table 9-4. MDM-AP Status register assignments (continued)Bit Name Description9 LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger willlose communication while the system is in LLS (including access to thisregister). Once communication is reestablished, this bit indicates that thesystem had been in LLS. Since the debug modules held their state duringLLS, they do not need to be reconfigured.This bit is set during the LLS recovery sequence. The LLS Mode Exit bit isheld until the debugger has had a chance to recognize that LLS was exitedand is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit inMDM AP Control register.10 VLLSx Modes Exit This bit indicates an exit from VLLSx mode has occurred. The debuggerwill lose communication while the system is in VLLSx (including access tothis register). Once communication is reestablished, this bit indicates thatthe system had been in VLLSx. Since the debug modules lose their stateduring VLLSx modes, they need to be reconfigured.This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exitbit is held until the debugger has had a chance to recognize that a VLLSmode was exited and is cleared by a write of 1 to the LLS, VLLSx StatusAcknowledge bit in MDM AP Control register.11 – 15 Reserved for future use Always read 0.16 Core Halted Indicates the Core has entered debug halt mode17 Core SLEEPDEEP Indicates the Core has entered a low power modeSLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode.SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode.18 Core SLEEPING19 – 31 Reserved for future use Always read 0.9.4 Debug ResetsThe debug system receives the following sources of reset:• Debug reset (CDBGRSTREQ bit within the DP CTRL/STAT register) that allowsthe debugger to reset the debug logic.• System POR resetConversely the debug system is capable of generating system reset using the followingmechanism:• A system reset in the DAP control register which allows the debugger to hold thesystem in reset.• SYSRESETREQ bit in the NVIC application interrupt and reset control register• A system reset in the DAP control register which allows the debugger to hold theCore in reset.Debug ResetsKL25 Sub-Family Reference Manual, Rev. 3, September 2012156 Freescale Semiconductor, Inc.
