33.4 Functional description33.4.1 LPTMR power and resetThe LPTMR remains powered in all power modes, including low-leakage modes. If theLPTMR is not required to remain operating during a low-power mode, then it must bedisabled before entering the mode.The LPTMR is reset only on global Power On Reset (POR) or Low Voltage Detect(LVD). When configuring the LPTMR registers, the CSR must be initially written withthe timer disabled, before configuring the PSR and CMR. Then, CSR[TIE] must be set asthe last step in the initialization. This ensures the LPTMR is configured correctly and theLPTMR counter is reset to zero following a warm reset.33.4.2 LPTMR clockingThe LPTMR prescaler/glitch filter can be clocked by one of the four clocks. The clocksource must be enabled before the LPTMR is enabled.NOTEThe clock source selected may need to be configured to remainenabled in low-power modes, otherwise the LPTMR will notoperate during low-power modes.In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input sourcedirectly clocks the CNR and no other clock source is required. To minimize power in thiscase, configure the prescaler clock source for a clock that is not toggling.NOTEThe clock source or pulse input source selected for the LPTMRshould not exceed the frequency fLPTMR defined in the devicedatasheet.33.4.3 LPTMR prescaler/glitch filterThe LPTMR prescaler and glitch filter share the same logic which operates as a prescalerin Time Counter mode and as a glitch filter in Pulse Counter mode.Chapter 33 Low-Power Timer (LPTMR)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 593
