Section number Title Page4.6.3 Modules Restricted Access in User Mode...................................................................................................1124.7 Private Peripheral Bus (PPB) memory map..................................................................................................................112Chapter 5Clock Distribution5.1 Introduction...................................................................................................................................................................1155.2 Programming model......................................................................................................................................................1155.3 High-Level device clocking diagram............................................................................................................................1155.4 Clock definitions...........................................................................................................................................................1165.4.1 Device clock summary.................................................................................................................................1175.5 Internal clocking requirements.....................................................................................................................................1195.5.1 Clock divider values after reset....................................................................................................................1195.5.2 VLPR mode clocking...................................................................................................................................1205.6 Clock Gating.................................................................................................................................................................1215.7 Module clocks...............................................................................................................................................................1215.7.1 PMC 1-kHz LPO clock................................................................................................................................1225.7.2 COP clocking...............................................................................................................................................1225.7.3 RTC clocking...............................................................................................................................................1235.7.4 LPTMR clocking..........................................................................................................................................1235.7.5 TPM clocking...............................................................................................................................................1245.7.6 USB FS OTG Controller clocking...............................................................................................................1245.7.7 UART clocking............................................................................................................................................125Chapter 6Reset and Boot6.1 Introduction...................................................................................................................................................................1276.2 Reset..............................................................................................................................................................................1276.2.1 Power-on reset (POR)..................................................................................................................................1286.2.2 System reset sources....................................................................................................................................1286.2.3 MCU Resets.................................................................................................................................................1316.2.4 Reset Pin .....................................................................................................................................................133KL25 Sub-Family Reference Manual, Rev. 3, September 20126 Freescale Semiconductor, Inc.
