UARTx_BDH field descriptions (continued)Field Description4–0SBRBaud Rate Modulo Divisor.The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for thebaud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) × BR).39.2.2 UART Baud Rate Register Low (UARTx_BDL)This register, along with UART _BDH, control the prescale divisor for UART baud rategeneration. The 13-bit baud rate setting [SBR12:SBR0] can only be updated when thetransmitter and receiver are both disabled.UART _BDL is reset to a non-zero value, so after reset the baud rate generator remainsdisabled until the first time the receiver or transmitter is enabled; that is, UART _C2[RE]or UART _C2[TE] bits are written to 1.Address: Base address + 1h offsetBit 7 6 5 4 3 2 1 0Read SBRWriteReset 0 0 0 0 0 1 0 0UARTx_BDL field descriptionsField Description7–0SBRBaud Rate Modulo DivisorThese 13 bits in SBR[12:0] are referred to collectively as BR. They set the modulo divide rate for the baudrate generator. When BR is 1 - 8191, the baud rate equals baud clock/((OSR+1) × BR).39.2.3 UART Control Register 1 (UARTx_C1)This read/write register controls various optional features of the UART system. Thisregister should only be altered when the transmitter and receiver are both disabled.Address: Base address + 2h offsetBit 7 6 5 4 3 2 1 0Read LOOPS DOZEEN RSRC M WAKE ILT PE PTWriteReset 0 0 0 0 0 0 0 0Register definitionKL25 Sub-Family Reference Manual, Rev. 3, September 2012726 Freescale Semiconductor, Inc.
