19.31.15 Component ID Register (MTB_COMPIDn)These registers indicate the component IDs. They are hardwired to specific values usedduring the auto-discovery process by an external debug agent.Address: F000_0000h base + FF0h offset + (4d × i), where i=0d to 3dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R COMPIDWReset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x** Notes:See field descriptions for the reset values.x = Undefined at reset.•MTB_COMPIDn field descriptionsField Description31–0COMPIDComponent IDComponent ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to0x0000_00B1.19.3.2 MTB_DWT Memory MapThe MTB_DWT programming model supports a very simplified subset of the v7M debugarchitecture and follows the standard ARM DWT definition.MTBDWT memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/pageF000_1000 MTB DWT Control Register (MTBDWT_CTRL) 32 R 2F00_0000h 19.32.1/317F000_1020 MTB_DWT Comparator Register (MTBDWT_COMP0) 32 R/W 0000_0000h 19.32.2/318F000_1024 MTB_DWT Comparator Mask Register (MTBDWT_MASK0) 32 R/W 0000_0000h 19.32.3/319F000_1028 MTB_DWT Comparator Function Register 0(MTBDWT_FCT0) 32 R/W 0000_0000h 19.32.4/320F000_1030 MTB_DWT Comparator Register (MTBDWT_COMP1) 32 R/W 0000_0000h 19.32.2/318F000_1034 MTB_DWT Comparator Mask Register (MTBDWT_MASK1) 32 R/W 0000_0000h 19.32.3/319F000_1038 MTB_DWT Comparator Function Register 1(MTBDWT_FCT1) 32 R/W 0000_0000h 19.32.5/322F000_1200 MTB_DWT Trace Buffer Control Register(MTBDWT_TBCTRL) 32 R/W 2000_0000h 19.32.6/323F000_1FC8 Device Configuration Register (MTBDWT_DEVICECFG) 32 R 0000_0000h 19.32.7/325Table continues on the next page...Memory Map and Register DefinitionKL25 Sub-Family Reference Manual, Rev. 3, September 2012316 Freescale Semiconductor, Inc.
