FTFA_FOPT [4,0] Core/system clock Bus/Flash clock Description00 0x7 (divide by 8) 0x1 (divide by 2) Low power boot01 0x3 (divide by 4) 0x1 (divide by 2) Low power boot10 0x1 (divide by 2) 0x1 (divide by 2) Low power boot11 0x0 (divide by 1) 0x1 (divide by 2) Fast clock bootThis gives the user flexibility in selecting between a lower frequency, low-power bootoption vs. higher frequency, higher power during and after reset.The flash erased state defaults to fast clocking mode, since these bits reside in flash,which is logic 1 in the flash erased state. To enable a lower power boot option, programthe appropriate bits in FTFA_FOPT. During the reset sequence, if either of the controlbits is cleared, the system is in a slower clock configuration. Upon any system reset, theclock dividers return to this configurable reset state.5.5.2 VLPR mode clockingThe clock dividers cannot be changed while in VLPR mode. They must be programmedprior to entering VLPR mode to guarantee operation. Max frequency limitations forVLPR mode is as follows :• the core/system clocks are less than or equal to 4 MHz, and• the bus and flash clocks are less than or equal to 1 MHzNOTEWhen the MCG is in BLPI and clocking is derived from theFast IRC, the clock divider controls (MCG_SC[FCRDIV],SIM_CLKDIV1[OUTDIV1], and SIM_CLKDIV1[OUTDIV4])must be programmed such that the resulting flash clock nominalfrequency is 800 kHz or less. In this case, one example ofcorrect configuration is MCG_SC[FCRDIV]=000b,SIM_CLKDIV1[OUTDIV1]=0000b andSIM_CLKDIV1[OUTDIV4]=100b, resulting in a divide by 5setting.Internal clocking requirementsKL25 Sub-Family Reference Manual, Rev. 3, September 2012120 Freescale Semiconductor, Inc.
