LPTMR memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 32 R/W 0000_0000h 33.3.1/5894004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 32 R/W 0000_0000h 33.3.2/5904004_0008 Low Power Timer Compare Register (LPTMR0_CMR) 32 R/W 0000_0000h 33.3.3/5924004_000C Low Power Timer Counter Register (LPTMR0_CNR) 32 R 0000_0000h 33.3.4/59233.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)Address: 4004_0000h base + 0h offset = 4004_0000hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 TCF TIE TPS TPP TFC TMS TENW w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPTMRx_CSR field descriptionsField Description31–8ReservedThis field is reserved.This read-only field is reserved and always has the value 0.7TCFTimer Compare FlagTCF is set when the LPTMR is enabled and the CNR equals the CMR and increments. TCF is clearedwhen the LPTMR is disabled or a logic 1 is written to it.0 The value of CNR is not equal to CMR and increments.1 The value of CNR is equal to CMR and increments.6TIETimer Interrupt EnableWhen TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.0 Timer interrupt disabled.1 Timer interrupt enabled.5–4TPSTimer Pin SelectConfigures the input source to be used in Pulse Counter mode. TPS must be altered only when theLPTMR is disabled. The input connections vary by device. See the chip configuration details forinformation on the connections to these inputs.00 Pulse counter input 0 is selected.Table continues on the next page...Chapter 33 Low-Power Timer (LPTMR)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 589
