I2Cx_A1 field descriptionsField Description7–1AD[7:1]AddressContains the primary slave address used by the I2C module when it is addressed as a slave. This field isused in the 7-bit address scheme and the lower seven bits in the 10-bit address scheme.0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.38.3.2 I2C Frequency Divider register (I2Cx_F)Address: Base address + 1h offsetBit 7 6 5 4 3 2 1 0Read MULT ICRWriteReset 0 0 0 0 0 0 0 0I2Cx_F field descriptionsField Description7–6MULTThe MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generatethe I2C baud rate.00 mul = 101 mul = 210 mul = 411 Reserved5–0ICRClockRatePrescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate,the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values correspondingto each ICR setting, see I2C divider and hold values.The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.I2C baud rate = bus speed (Hz)/(mul × SCL divider)The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C data).SDA hold time = bus period (s) × mul × SDA hold valueThe SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (startcondition) to the falling edge of SCL (I2C clock).SCL start hold time = bus period (s) × mul × SCL start hold valueThe SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2Cdata) while SCL is high (stop condition).SCL stop hold time = bus period (s) × mul × SCL stop hold valueFor example, if the bus speed is 8 MHz, the following table shows the possible hold time values withdifferent ICR and MULT selections to achieve an I2C baud rate of 100 kbps.Table continues on the next page...Chapter 38 Inter-Integrated Circuit (I2C)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 691
