2. Write to C1 register to select the clock mode.• If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit toswitch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that theoutput of the FLL is selected as the system clock source.• If entering FBE, clear the C1[IREFS] bit to switch to the external reference andchange the C1[CLKS] bits to 2'b10 so that the external reference clock isselected as the system clock source. The C1[FRDIV] bits should also be setappropriately here according to the external reference frequency to keep the FLLreference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL isbypassed, it is still on in FBE mode.• The internal reference can optionally be kept running by setting theC1[IRCLKEN] bit. This is useful if the application will switch back and forthbetween internal and external modes. For minimum power consumption, leavethe internal reference disabled while in an external clock mode.3. Once the proper configuration bits have been set, wait for the affected bits in theMCG status register to be changed appropriately, reflecting that the MCG has movedinto the proper mode.• If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS0] wasalso set in step 1, wait here for S[OSCINIT0] bit to become set indicating thatthe external clock source has finished its initialization cycles and stabilized.• If in FEE mode, check to make sure the S[IREFST] bit is cleared before movingon.• If in FBE mode, check to make sure the S[IREFST] bit is cleared and S[CLKST]bits have changed to 2'b10 indicating the external reference clock has beenappropriately selected. Although the FLL is bypassed, it is still on in FBE mode.4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequencyrange.• By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCOoutput is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequencyof 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set theC4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a high-range FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to2'b11 for a DCO output frequency of 80 MHz.Initialization / Application informationKL25 Sub-Family Reference Manual, Rev. 3, September 2012392 Freescale Semiconductor, Inc.
