23.4.2 Channel Initialization and StartupBefore a data transfer starts, the channel's transfer control descriptor must be initializedwith information describing configuration, request-generation method, and pointers to thedata to be moved.23.4.2.1 Channel PrioritizationThe four DMA channels are prioritized based on number, with channel 0 having highestpriority and channel 3 having the lowest, that is, channel 0 > channel 1 > channel 2 >channel 3.Simultaneous peripheral requests activate the channels based on this priority order. Onceactivated, a channel runs to completion as defined by DCRn[CS] and BCRn.23.4.2.2 Programming the DMA Controller ModuleCAUTIONDuring a channel's execution, writes to programming modelregisters can corrupt the data transfer. The DMA module itselfdoes not have a mechanism to prevent writes to registers duringa channel's execution.General guidelines for programming the DMA are:• TCDn is initialized.• SARn is loaded with the source (read) address. If the transfer is from aperipheral device to memory or to another peripheral, the source address is thelocation of the peripheral data register. If the transfer is from memory to aperipheral device or to memory, the source address is the starting address of thedata block. This can be any appropriately aligned address.• DARn is initialized with the destination (write) address. If the transfer is from aperipheral device to memory, or from memory to memory, DARn is loaded withthe starting address of the data block to be written. If the transfer is frommemory to a peripheral device, or from a peripheral device to a peripheraldevice, DARn is loaded with the address of the peripheral data register. Thisaddress can be any appropriately aligned address.Functional DescriptionKL25 Sub-Family Reference Manual, Rev. 3, September 2012362 Freescale Semiconductor, Inc.
