• Destination address field set to bits[31:1] of the EXC_RETURN value. See theARM v6-M Architecture Reference Manual.• The A-bit set to 0.• The second packet has the:• Source address field set to bits[31:1] of the EXC_RETURN value.• Destination address field set to the address of the instruction where executioncommences.• A-bit set to 1."Given the recorded change-of-flow trace packets in system RAM and the memory imageof the application, a debugger can read out the data and create an instruction-by-instruction program trace. In keeping with the low area and power implementation costdesign targets, the MTB trace format is less efficient than other CoreSight trace modules,for example, the ETM (Embedded Trace Macrocell). Since each branch packet is 8 bytesin size, a 1 KB block of system RAM can contain 128 branches. Using the Dhrystone 2.1benchmark's dynamic runtime as an example, this corresponds to about 875 instructionsper KB of trace RAM, or with a zero wait state memory, this corresponds toapproximately 1600 processor cycles per KB. This metric is obviously very sensitive tothe runtime characteristics of the user code.The MTB_DWT function (not shown in the core platform block diagram) monitors theprocessor address and data buses so that configurable watchpoints can be detected totrigger the appropriate response in the MTB recording.19.1.2 FeaturesThe key features of the MTB_RAM and MTB_DWT include:• Memory controller for system RAM and Micro Trace Buffer for program tracepackets• Read/write capabilities for system RAM accesses, write-only for program tracepackets• Supports zero wait state response to system bus accesses when no trace data is beingwritten• Can buffer two AHB address phases and one data write for system RAM accesses• Supports 64-bit program trace packets including source and destination instructionaddresses• Program trace information in RAM available to MCU's application code or externaldebugger• Program trace watchpoint configuration accessible by MCU's application code ordebugger• Location and size of RAM trace buffer is configured by softwareIntroductionKL25 Sub-Family Reference Manual, Rev. 3, September 2012302 Freescale Semiconductor, Inc.
