When configured for PSTOP1, both the system clock and bus clock are gated. All busmasters and bus slaves enter Stop mode, but the clock generators in the MCG and the on-chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can beinitiated by a reset or an asynchronous interrupt from a bus master or bus slave. Ifconfigured, an asynchronous DMA request can also be used to exit Partial Stop for theduration of a DMA transfer before the device is transitioned back into PSTOP1.PSTOP1 is functionally similar to STOP mode, but offers faster wakeup at the expense ofhigher power consumption. Another benefit is that it keeps all of the MCG clocksenabled, which can be useful for some of the asynchronous peripherals that can remainfunctional in Stop modes.7.2.2 DMA WakeupThe DMA can be configured to wakeup the device on a DMA request whenever it isplaced in stop mode. The wakeup is configured per DMA channel and is supported inCompute Operation, PSTOP, STOP and VLPS low power modes.When a DMA wakeup is detected in PSTOP, STOP or VLPS then the device will initiatea normal exit from the low power mode. This can include restoring the on-chip regulatorand internal power switches, enabling the clock generators in the MCG, enabling thesystem and bus clocks (but not the core clock) and negating the stop mode signal to thebus masters and bus slaves. The only difference is that the CPU will remain in the lowpower mode with the CPU clock disabled.During Compute Operation, a DMA wakeup will initiate a normal exit from ComputeOperation. This includes enabling the clocks and negating the stop mode signal to the busmasters and bus slaves. The core clock always remains enabled during ComputeOperation.Since the DMA wakeup will enable the clocks and negate the stop mode signals to all busmasters and slaves, software needs to ensure that bus masters and slaves that are notinvolved with the DMA wakeup and transfer remain in a known state. That can beaccomplished by disabling the modules before entry into the low power mode or bysetting the Doze enable bit in selected modules.Once the DMA request that initiated the wakeup negates and the DMA completes thecurrent transfer, the device will transition back into the original low power mode. Thisincludes requesting all non-CPU bus masters to enter Stop mode and then requesting busslaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would thenalso enter their appropriate modes.Clocking ModesKL25 Sub-Family Reference Manual, Rev. 3, September 2012138 Freescale Semiconductor, Inc.
