6.2.3.6 Chip ResetChip Reset asserts on all reset sources and only negates after flash initialization hascompleted and the RESET pin has also negated. It resets the remaining modules (themodules not reset by other reset types).6.2.4 Reset PinFor all reset sources except a VLLS Wakeup that does not occur via the RESET pin, theRESET pin is driven low by the MCU for at least 128 bus clock cycles and until flashinitialization has completed.After flash initialization has completed, the RESET pin is released, and the internal ChipReset negates after the RESET pin is pulled high. Keeping the RESET pin assertedexternally delays the negation of the internal Chip Reset.The RESET pin can be disabled by programming RESET_PIN_CFG option bit to 0.When this option is selected, there could be a short period of contention during a PORramp where the device drives the pin out low prior to establishing the setting of thisoption and releasing the RESET function on the pin.6.2.5 Debug resetsThe following sections detail the debug resets available on the device.6.2.5.1 Resetting the Debug subsystemUse the CDBGRSTREQ bit within the DP CTRL/STAT register to reset the debugmodules. However, as explained below, using the CDBGRSTREQ bit does not reset alldebug-related registers.CDBGRSTREQ resets the debug-related registers within the following modules:• SW-DP• AHB-AP• MDM-AP (MDM control and status registers)CDBGRSTREQ does not reset the debug-related registers within the following modules:• CM0+ core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)• BPUChapter 6 Reset and BootKL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 133
