17.3 Memory Map and Register DefinitionThe BME module provides a memory-mapped capability and does not include anyprogramming model registers. The exact set of functions supported by the BME aredetailed in the Functional Description.The peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000plus a 4 KB space based at 0x400F_F000 for GPIO accesses; the decorated address spaceis mapped to the 448 MB region located at 0x4400_0000 - 0x5FFF_FFFF.17.4 Functional DescriptionThis section details the specific functions supported by the BME.Recall the combination of the basic load and store instructions of the Cortex-Minstruction set architecture (v6M, v7M) plus the concept of decorated storage provided bythe BME, the resulting implementation provides a robust and efficient read-modify-writecapability to this class of ultra low-end microcontrollers. The resulting architecturalcapability defined by this core platform function is targeted at the manipulation of n-bitfields in peripheral registers and is consistent with I/O hardware addressing in theEmbedded C standard. For most BME commands, a single core read or write bus cycle isconverted into an atomic read-modify-write, that is, an indivisible "read followed by awrite" bus sequence.Consider decorated store operations first, then decorated loads.17.4.1 BME Decorated StoresThe functions supported by the BME's decorated stores include three logical operators(AND, OR, XOR) plus a bit field insert. For all these operations, BME converts a singledecorated AHB store transaction into a 2-cycle atomic read-modify-write sequence,where the combined read-modify operation is performed in the first AHB data phase, andthen the write is performed in the second AHB data phase.A generic timing diagram of a decorated store showing a bit field insert operation isshown as follows:Memory Map and Register DefinitionKL25 Sub-Family Reference Manual, Rev. 3, September 2012274 Freescale Semiconductor, Inc.
