Table 38-41. I2C divider and hold values (continued)ICR(hex)SCLdividerSDA holdvalueSCL hold(start)valueSCL hold(stop)valueICR(hex)SCLdivider(clocks)SDA hold(clocks)SCL hold(start)valueSCL hold(stop)value14 80 17 34 41 34 1152 193 574 57715 88 17 38 45 35 1280 193 638 64116 104 21 46 53 36 1536 257 766 76917 128 21 58 65 37 1920 257 958 96118 80 9 38 41 38 1280 129 638 64119 96 9 46 49 39 1536 129 766 7691A 112 17 54 57 3A 1792 257 894 8971B 128 17 62 65 3B 2048 257 1022 10251C 144 25 70 73 3C 2304 385 1150 11531D 160 25 78 81 3D 2560 385 1278 12811E 192 33 94 97 3E 3072 513 1534 15371F 240 33 118 121 3F 3840 513 1918 192138.4.2 10-bit addressFor 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.Various combinations of read/write formats are possible within a transfer that includes10-bit addressing.38.4.2.1 Master-transmitter addresses a slave-receiverThe transfer direction is not changed. When a 10-bit address follows a START condition,each slave compares the first 7 bits of the first byte of the slave address (11110XX) withits own address and tests whether the eighth bit (R/W direction bit) is 0. It is possible thatmore than one device finds a match and generates an acknowledge (A1). Each slave thatfinds a match compares the 8 bits of the second byte of the slave address with its ownaddress, but only one slave finds a match and generates an acknowledge (A2). Thematching slave remains addressed by the master until it receives a STOP condition (P) ora repeated START condition (Sr) followed by a different slave address.Chapter 38 Inter-Integrated Circuit (I2C)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 707
